Design Tools - Others

[deba_techno]

i am using chip scope pro 12.3.i take "yout" in my design program as output which is 32 bit. i heve assign also the pin (using virtex 4,assigning the pin no watching the respective manual of virtex 4 pin assignment) for yout(0)...................yout(31). but in chip scope pro i get the trigger input along with other input,can't find yout.plz help.

[jschimek]

Deba_techno,

Its not entirely clear what you are trying to do here from me.  From what I am reading, you are having trouble hooking non-loc'ed pins to chipscope.  One tip, I would say is to look at the RTL view to ensure the net exists.  Also be careful not to connect between OBUF and pad..

Regards,

Jon

[deba_techno]

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jschimek wrote:

Deba_techno,

Its not entirely clear what you are trying to do here from me.  From what I am reading, you are having trouble hooking non-loc'ed pins to chipscope.  One tip, I would say is to look at the RTL view to ensure the net exists.  Also be careful not to connect between OBUF and pad..

Regards,

Jon

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sir, i tried to test the output of my design which i have implemented in data flow model. in "netlist" i have not found the output of my design. this is my problem.i have assigned the output pins following the virtex 4 pin  configuration sheet, and assigned those to i/o pins. in my program,there was clk signal, (which i have inserted later,bcoz in chipscopepro there is a clk assignment net ) but no reset signal.  i don't understand why i did not get thost output. if reset and clk are mandatory to test the output through chipscopepro??

[cribbing]

Try looking at the synthesis report file. Likely there will be some messages in there that explains why the tool is optimizing those nets out. My guess is that they are unconnected in your design

[deba_techno]

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cribbing wrote:
Try looking at the synthesis report file. Likely there will be some messages in there that explains why the tool is optimizing those nets out. My guess is that they are unconnected in your design

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 Thank you sir, positively i will look it. but my doubt regarding chipscope pro is, does it test any program which has no clk and reset signal .plz ans.

[viviany]

You do need a clock net for Chipscope because Chipscope logics are synchronous circuits and need a capture clock. But a reset is not necessary.

The lack of clock and reset signal may not be the cause of your output signals being removed. As cribbing stated, you should check your synthesis report for messages mentioning these signals being removed. These messages may give you hints on why they are removed.

Vivian