Digital Signal Processing - IP and Algorithms

[sushantm]

Hi All,

I want to convert output of ADV7180 which is 8-bit ITU-R BT.656 YCrCb 4:2:2 into rgb for some processing on TI's Da-Vinci DM8168 device through PCIe interface.

found the Xilinx color space converter ip core.

--> Selected the Standard as ITU 601.

-->Input range selection is 16 to 240 for TV.

-->Precision settings are

--> Input data width is set to 8 bit.

--> output data width is set to 8 bit.

-->coefficient bits to 18 bits.

although when I generate the IP core I see video data in is 24 bit and output video is also of 24 bit.

I have a custom FIFO module in which we have 8bit in and 64 bit out interface.

My question is how I should convert 8 bit ycrcb4:2:2 o/p of ADV7180 in to 24 bit for the IP core to work and give me 8 bit rgb output so that i can store in FIFO having 8 bit input interface.

Can I generate IP core with 8 bit ycrcb input and 8 bit rgb output ?

Please suggest with the right path.

Links would be helpful.

Thanks in advance!

[gszakacs]

The 8 bit data you receive has an interleaved pattern like Y Cr Y Cb Y Cr Y Cb . . .

From that pattern, you need to do some filtering to generate a Cr and Cb for

each Y (Y is the luminance or greyscale portion of the image at each pixel site).

Wikipedia has a page on chroma subsampling at:

http://en.wikipedia.org/wiki/YUV_4:2:2

And there is a detailed article on method of subsampling at:

http://dougkerr.net/pumpkin/articles/Subsampling.pdf

Basically, there is more than one way to subsample the chroma (color) signals

and that affects the optimum way to filter them to create the "cosited" value

for each pixel.  You should also look at the data sheet for your ADV7180 to

see if it describes the type of subsampling it uses.

Also note that ITU-R BT.656 contains header information for each line of

the image as well as the frame.  The document is available from the ITU,

but it's not free.

-- Gabor

[austin]

S,

Why do you have a custom FIFO module, when the parts have built-in perfectly good working FIFO's?

Why not use the built in FIFO's?

Next, it is easier to convert the 24 bit format to another format, as the IP core is designed to meet a standard, and it is unlikely there are any options at all for widths (if you haven't found them, they are not there).  Seems you need to convert from one standard to another, or perhaps go find the converter for the standard you need?

http://www-mtl.mit.edu/Courses/6.111/labkit/appnotes/xapp286_04.pdf

http://cegt201.bradley.edu/projects/proj2009/rtvcips/index_files/Funcional_Description.pdf

http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5460530

http://www.eetkorea.com/ARTICLES/2004JUN/2004JUN22_PLD_RFD_AN04.PDF?SOURCES=DOWNLOAD

inst.eecs.berkeley.edu/~cs150/sp07/Lectures/11-VideoConference.ppt

[sushantm]

Gabor & Austin thanks a ton!

---

austin wrote : Why do you have a custom FIFO module, when the parts have built-in perfectly good working FIFO's?

                           Why not use the built in FIFO's?

---

erringly wrote.my apologizes!

We are using built-in fifos only inside virtex-6.

Both of you thanks again for the links!

I'll get back to you!