Digital Signal Processing - IP and Algorithms

[polyee13]

I am using the dds 4.0 core with the following attributes.  27.5MHz, phase width 19 bits, output 16 bits.

If I set my phase increment to 8A I should expect a frequency of 7.238KHz.  However, in my ModelSim simulation I am seeing double that frequency.  However, if I halve the phase increment to 45h then I get my desired frequency. What is going on? Thanks. 

[ywu · Accepted solution]

My guess is that the input clock used in the simulation is 55MHz (2x 27.5MHz). Can you post the waveform showing the input clock frequency and how the phase increment is set?

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polyee13 wrote:

I am using the dds 4.0 core with the following attributes.  27.5MHz, phase width 19 bits, output 16 bits.

If I set my phase increment to 8A I should expect a frequency of 7.238KHz.  However, in my ModelSim simulation I am seeing double that frequency.  However, if I halve the phase increment to 45h then I get my desired frequency. What is going on? Thanks. 

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[polyee13]

Issue resolved.  After regenerating the core with 27.5MHz I didn't replace the files correctly in my simulation directory.