Digital Signal Processing - IP and Algorithms

[arash-rezaee]

Hi

I am using divider ip core for my project. I am using spartan 3E and ISE 12.1. Dividend is 16 bit and divisor is 16 bit. I am using fractional mode. When I divide for example 1000 by 1000 I can get results from Quotient which is 1. But when dividend is 500 and divide it by 1000 from fractional output I can get "1000000000000000"b. I know it is correct also which represent 0.5 in decimal if I convert it. I connected fractional output to another block which the input is 16 bit STD_LOGIC_vector(15 downto 0). My question how can I use outputs of Divider core in purpose of multiply it in other block. I mean when I have for example 11555 and I divide it with 1000, I will have 11.555 and I want to multiply this value in other block with one STD_LOGIC_VECTOR. How can I figure out 11.555 in other block with help of quotient and fractional output.

I hope, my explanation is fine and some one help me.

Regards

[vlavruhin]

Hi.

If all numbers are unsigned, then you can concatenate the bits of Quotinent and Fractional, thus getting fixed-point fractional number.

Suppose that Q(n-1), Q(n-2), ..., Q(0) is Quotient and F(m-1), F(m-2), ..., F(0) is Fractional. Then

Q(n-1), Q(n-2), ..., Q(0), F(m-1), F(m-2), ..., F(0) is fixed-point fractional number with (n+m) total bits and m fractional bits (format UFix_(n+m)_m).

If you need to truncate it, then you can drop some MSBs of Quotient and some LSBs of Fractional.