Digital Signal Processing - IP and Algorithms

[bracchetto]

yes.. it is.. i have take a look at this CIC filter.. they are very intersting but from what i can read i have to think about also how to compensate they behavior, well this can be solved inside the filtering,  but anyway they allow to increase or decrese frequency.. but actually my signal bandwith cover almost al the sampling spectrum (from 0.2 to 0.7) but i don´t need to slow down frequency and neither go up.

In these day i have manage to double the filter clock, so i reach now a filter of 128taps of lenght using 528dpsp working at 271Mhz. I am wonder if this could be enough or i should double the clock one more time so I can reach a filter lenght of 256taps. Is there any formula that links the filter lenght with the ability of compensation?

[eilert]

Hi,

the best result will always be acheived with a FIR-filter of infinite lenght.

Only drawback is that at this length you will never see any result at all. ;-)

No matter what filter you will use, it can always only be an approximation to the optimal result.

Not just that the complexity of the inverse transfer funktion of your analog parts might be difficult to create, but it also might change over time, (e.g. due to temperatue humidity or aging). These effects can't be compensated with a simple filter. The keyword to face these problems is "adaptive filtering", but this neither make things simpler, nor guarantees better results in all cases. 

You are working with a very high bandwidth. Are the signals equally distributed within this frequency range? Can you divide it into subbands? A smaller subband may have a less complex transfer function and so better results might be achieved with a smaller filter.

You are trying to solve a complex problem with a very straight forward approach. The problem with that is that this way often leads to very ressource hungry solutions. (e.g. I was trying to create some narrow Band pass filter. With FIR it had a ridiculously high order, changing to IIR reduced the order to below 20. The big drawback: There is no IIR Compiler in the Xilinx IP collection, so I had to design/draw/code it all by myself.)

Maybe there are other approaches to your problem that give an acceptable result with less ressource demand.

Have a nice synthesis

  Eilert

[bracchetto]

Hi, thank you very much for your help, you guess the goal of the project.. compensate temperature and aging effect on the analog part.

why do you say that a simple filter cannot compensate for these effect?

I can estimate the all analog part and compute the filter coefficient and then apply it.
(this is done in python :) )

the system doesn´'t have to behave with a perfectly flat frequency response.. some ripples are tollerated, but they have to stay within a certain amount.

the signal cover all the bandwitdth with the same amplitude, from 200Mhz to 800Mhz, it is like a chirp function.

well, the resource are not a problem.. the only thing this fpga has to do is processing this signal.. so i can use almost every single flip flop :)

IIR filter are quite problematic, first because of the non linearity of the phase and then also the computation of the coefficente is more complex.

[eilert]

Hi,

if you want to compensate temperature and aging effects, you need to determine the TF (transfwr function) of the analog part over time, as it changes. Then invert it and calculate the FIR coefficients.  Can your system do this automatically? In that case you already have some sort of adaptive filter.

So how do you estimate the temperature changes of your analog part during runtime?

You surely can do min/max calculations and check wether the signal is still within the field of tolerance, but the changes in the signal caused by some effect can not be eliminated this way.

(Or is it just for some short time running lab experiment?)

The example with the IIr was just meant to show how a differnt approachcan change the ammount of hardware needed. Of course nothing comes for free, as you mention the nonlinear phase properties. But for some applications this might not be a problem. And for calculating the coefficients, well thats clicking one button in the Matlab FDA-Tool to switch between FIR and IIR for a standard filter. In your case it might be different.

But this was just intended to be a generic example, not a useful alternative for your problem.

Have a nice synthesis

  Eilert

[bracchetto]

Hi,

yes yes the system can do this, basically the system goes in a calibration mode and  generate a signal that cover all the bandwith, the signal pass thoruhg all the analog component and it is recorded.  Now the channel estimation is very rough.. i just took the ratio between the fft of the transmitted signal and the fft of the received signal

then filter coefficent are  computed and applyed to the filter, and then the system goes back in runtime mode.

so the filter has to take care of equalizing the analog component and also all the changes due to temperature or aging

[eilert]

Hi,

well, that's great. Maybe you should have mentioned that before.

It's quite hard to be helpful if only a part of the system is explained but influenced or depending on other parts.

Since the estimation is done with a python script, I suspect that there's some heavy CPU involved as well (at least some ARM if not x86/x64) beside the FPGA.

But if you say that the channel estimation is very rough anyway, how can you expect the TF-linearization done with the FIR to be any better than that? Or is your estimation still better than what you could acheive with a 64 or 128 tap FIR?

And if you are doing FFT for the estimation, why aren't you using a similar FFT/IFFT combination for the FPGA too.

In that case you could directly apply the gain coefficients for the different frequency samples, without the need to calculate FIR-Coefficients. But probably the FFT used fo the estimation is too big to fit into an FPGA for a real time application.

Have a nice synthesis

  Eilert

[bracchetto]

hi, yes.. beside the fpga there is a linux server that can be used for doing the needed processing,

but when in runtime mode the system must be real time, so it not possibile to perform the fft on the fpga.

the channel estimation is rough, with this i wanted to mean that there should be other way to estimate the channel in a better way.. but it is still a problem that i have to solve.. but anyway.. for now it is ok, i can compensate for some ripple that are present in the channel..

i have read something about  FIR Least squares inverse Filter  that seems to fit very well to my problem