Digital Signal Processing - IP and Algorithms

[spouros]

Hello,

I am new to the Xilinx FPGA products. I have a Virtex 5 board and I want to implement this scenario. I need professional guidelines to implement it.

I will have an 8-bit parallel input (clk at 27MhZ) from 8 pins of the board ML505. The input will be a sine wave signal from an ADC. I need to filter the signal (FIR Low Pass at  fc=2khz) and then create and output as an 8 bit signal to 8 pins of the board followed by  a DAC.

So far:

I have implemented part of the project in Simulink using System Generator (working) but I used a random source as an input and as an output a spectrum analyser.

Questions: What should I do with the 8bit  input data to send them to the FIR Compiler and how can I convert the output data of the FIR Compiler 5.0 to the desired 8 bit parallel output to the DAC.

Thank you in advance for your time,

I am grateful,

[eilert]

Hi,

you need to add "Gateway In" and "Gateway Out" blocks to the I/Os of your design. They do the necessary conversions.

Since you already have somehow splitted your signals into 8 bit (instead of using simple double type numbers (Matlab standard), you might need to combine/expand them by some additional blocks from the Xilinx Blockset. (e.g. such as Concat and Slice)

But if your problems are so basic, you might read the sysgen "Getting Started Guide" (UG639) first, to understand the procedures used in this kind of design flow.

Otherwise you will get stuck with your project over and over again.

Have a nice simulation

  Eilert