Digital Signal Processing - IP and Algorithms

[yangli]

I use the fir core to generate a halfband filter. So, here are the signals :

//  Instantiate the module
hb unit_hb(
rfd(rfd_hb8_i), 
.rdy(rdy_hb8_i), 
.clk(clk_32_768m), 
.dout(data_hb8_i), 
.din(data_hb_i_inr)
)
//hb 的输入在 rfd置位时,数据要稳定 所以以其下降沿将输入锁存送入
// at the fall edge of rfd,i  put the value of data_cic_i_outr into //register then to the inport
	 always @(negedge rfd_hb8_i)
	      if(reset)
			   data_hb8_i_inr <= 0;
		   else
	        data_hb8_i_inr <= data_cic_i_outr;
	
	

but the output dout has a xxxxx value , I'll appreciate it if anyone can help me. many thanks

[ywu]

Can you attach a picture showing waveforms of all signals to/from the half band filter?

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yangli wrote:

I use the fir core to generate a halfband filter. So, here are the signals :

//  Instantiate the module
hb unit_hb(
rfd(rfd_hb8_i), 
.rdy(rdy_hb8_i), 
.clk(clk_32_768m), 
.dout(data_hb8_i), 
.din(data_hb_i_inr)
)
//hb 的输入在 rfd置位时,数据要稳定 所以以其下降沿将输入锁存送入
// at the fall edge of rfd,i  put the value of data_cic_i_outr into //register then to the inport
	 always @(negedge rfd_hb8_i)
	      if(reset)
			   data_hb8_i_inr <= 0;
		   else
	        data_hb8_i_inr <= data_cic_i_outr;
	
	

but the output dout has a xxxxx value , I'll appreciate it if anyone can help me. many thanks

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