Digital Signal Processing - IP and Algorithms

[embedded]

Hi all,

I am using ISE12.4 and I have implemented an FIR block into my SP3A DSP. When I simulate my design I see that two first output samples are nearly the full range of my FIR output - despite correct values of input - and then it settles down and follows correct and expected outputs,

I want to see if this is a common bug in FIR or I have something wrong with it.

I should add that as I don't see it in the next reset de-activation I can safely overlook it but I want to know the source of issue and fix the bug if it is in my side.

Thanks,

Hossein Moradi Sarvandi

[bwiec]

Hello Hossein

Is it possible for you to post a screenshot of the behavior?

[embedded]

Hi,

FIR output signal is a 25 bit width and the first two samples are near full range - 0x1FFF1BC0, 0X1FFA130- then go to the acceptable values.

Two waveforms are output of FIR and decimated one and I selected analog display format for them, signal waveform is a teletext data if you are familiar with. as you can see at the begining of the wavefrom we have a very high pulse. I should add that this fenamenan is appeared once on the FIR output and after other reset activities it is operating properly.

I just want to know the reason.

Regards,

Hossein Moradi Sarvandi

[embedded]

Hi, I think I need to declare some points about my observation, I am using an Interpolation FIR core with interpolation rate of 72. When I looked at the outputs I saw that there are many saturated samples in the output.nearly those first 72 samples. What may has caused to such behavior? I appreciate any help. Hossein

[chrisar]

It's kind of hard to tell from your example, but are you sure that the output of the FIR Compiler is marked as valid, during these first few outputs?

Also have you reviewed the known issues list for this core?

http://www.xilinx.com/support/answers/29138.htm