Digital Signal Processing - IP and Algorithms

[yasirmahmoodqureshi]

I have just started to work on fft ip core, I am new to Xilinx ise, So can any one help where to get started with the fft ip core

[vytautas · Accepted solution]

Hello. FFT IP core you can generate with CoreGenerator (tools of ISE).

 In this forum I have several discusion such topic about. For example here:

http://forums.xilinx.com/xlnx/board/message?board.id=DSP&thread.id=563

 I generate this pcore and try to implement it in MicroBlaze connecting per FSL bus.

[yasirmahmoodqureshi]

Thanks Vytautas

Regards

Yasir

[dudovitz]

Hey there. 

I've got pretty much the same problem but I actually didn't want to implement the FFT via Microblaze. Is the IpCore FFT generally a microblaze implementation or is there a possibility to just implement the FFT as a vhdl-code? 

Untill now I created a new project for the Spartan 3 FPGA ( XC3S200 ) and generated the IpCore FFT. Now I can't figure out how to use this in my vhdl-code. Does anybody know a tutorial or so? 

Thanks in advance.

Len 

[vlavruhin]

Hi, Len.

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Is the IpCore FFT generally a microblaze implementation or is there a possibility to just implement the FFT as a vhdl-code?

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First of all, LogiCORE IPs are designed for use in HDL projects. And FFT IP is no exception.

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Untill now I created a new project for the Spartan 3 FPGA ( XC3S200 ) and generated the IpCore FFT. Now I can't figure out how to use this in my vhdl-code. Does anybody know a tutorial or so?

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1. Create new VHDL project in Xilinx ISE.
2. Add 'New Source' to it. Choose IP -> Digital Signal Processing -> Transforms -> FFTs -> Fast Fourier Transform.

3. Set desired options of core and generate it.

4. Select in ISE Hierarchy View (upper left corner) your FFT core. Then in Processes View (lower) click on CORE Generator -> View HDL Instantiation Template.

5. Now you should be able to see Instantiation Template. It is file named 'YOUR_CORE_NAME.VHO'. Also you can find it manually by looking in 'YOUR_PROJECT_FOLDER\IPCORE_DIR'.

6. Add 'New Source' to the project, choose VHDL module. Insert there parts of Instantiation Template.

7. Now you can add your own testbenches and simulate core.

There is a detailed description of parameters of FFT IP core in following document:

http://www.xilinx.com/support/documentation/ip_documentation/xfft_ds260.pdf

[dudovitz]

Wuhuuu there it is. Thank you very much Vitaly! Now I got something to work with. 

Thanks again!

Regards,

Len