04-19-2012 10:53 AM
Hi, In my simulation, some floating points data samples are initialized in a simple dual port block ram.
The port B (read only, 64 bit width) of block ram is then connected directly to FFT ip core V7.1
Same clock signal for FFT and block ram.
connections are as follows.
-----FFT ports--------Block RAM ports-----
xn_index -> addrb
xn_re <- datab( 63 downto 32)
xn_im <- datab( 31 downto o)
The FFT computation result is some how corresponds to a shifted version of block ram samples.
In other words, when the FFTcore trys to obtain a Nth sample , it gets the (N+1)th.
Why is this happening and how should I solve it?
04-19-2012 12:22 PM
Sounds like you have a cycle of read latency in your BRAM configuration.
Have you simulated this? By probing the appropriate signals, you should be able to find out exactly what's happening.
04-20-2012 06:20 AM
You'll have to add some logic to handle the delay if it is important in your application. Try connecting the address port of the BRAM to addrb+1 (which is the equivalent of xn_index+1). You'll have to handle the boundary cases, though.