Digital Signal Processing - IP and Algorithms

[viswa_1981]

Hi,

I am facing an issue in FPGA.I am expecting some solution on the following problem.

how do we write program to interface the data stored in FIFO to FFT core in virtex 5 fpga  compute and again send back to external static ram(sram)

please assist me.

[bassman59]

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viswa_1981 wrote:

Hi,

I am facing an issue in FPGA.I am expecting some solution on the following problem.

how do we write program to interface the data stored in FIFO to FFT core in virtex 5 fpga  compute and again send back to external static ram(sram)

please assist me.

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First, you need to design a FIFO, or use an existing design. Then you need to figure out how to get data into it. Then you need to design an FFT engine, or use an existing design, and then figure out how to connect its inputs to the FIFO outputs. Then you need to design an interface to the external SRAM, and then figure out how to connect that interface to the FFT engine's outputs.

Seems pretty simple and straightforward to me.

[klumsde]

Xilinx provides a BRAM/FIFO generator in Coregen. 

It can instantiate a FIFO for you in your design. 

You should also look at the IP catalog to see if there is an FFT IP that suits your purpose. 

Then there is the MIG(Memory interface GUI) this can instance in a memory controller and interface to communicate with your SRAM.