Digital Signal Processing - IP and Algorithms

[eilert]

Hi,

I attempted to build some really large FIR Lowpass filter with FIR-Compiler 5.0.

It is of 219th order, so I expected it to fit into the V5SX50 with its 266 DSP48 Macros.

During netlist generation the following error message appared:

"Core requires more DSP48 elements (71) than are available in a single column in the selected device (48)"

What causes this limitation?

How can it be overcome?

Please let me know if any information from reports etc. is needed to analyze this issue.

Regards

  Eilert

[ywu]

The limitation is that DSP48s are organized in columns and within each DSP48 column there is dedicated and fast connection for PCIN and PCOUT ports between adjacent DSP48s (see the vertical routes between blue blocks below). FIR compiler uses this connection to achieve the highest performace for symmetric FIR filters.

The good news is that the support of multiple DSP48 columns for symmetric FIR filters is being worked on and should be available soon. For now, there are several workarounds you may consider:

• If you change the coefficient structure to "Non Symmetric", you can then change the option for "Multiple Column Support". Please note this will use a lot more DSP48's, but it doesn't look like a concern for this particular design.
• Double the frequency of the clock driving the FIR block, which will reduce the number of DSP48's by half. Of course this is only possible if the double clock frequnecy is still within the operating limit of various components
• Create your own FIR filter in RTL (shouldn't be too difficult)
• Break the one big filter into two smaller ones.

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eilert wrote:

Hi,

I attempted to build some really large FIR Lowpass filter with FIR-Compiler 5.0.

It is of 219th order, so I expected it to fit into the V5SX50 with its 266 DSP48 Macros.

During netlist generation the following error message appared:

"Core requires more DSP48 elements (71) than are available in a single column in the selected device (48)"

What causes this limitation?

How can it be overcome?

Please let me know if any information from reports etc. is needed to analyze this issue.

Regards

  Eilert

---

[ywu]

Please see the edited reply above.

[ywu]

Please see the edited reply above.

[eilert]

Hi Jim,

thanks fo the hints, I will try them.

Using more DSM48 Macros is no problem for me.

I'm working on some presentation example for HW-Cosimulation, so the design is intended to be big.

Something similar to lab7 of the sysgen Getting Started Guide, just that I need to do it for a ml506 board with a V5 device.

I tried with some smaller FIR to avoid the limitation temporarily, but it seems that the netlister is somewhat broken ("Formal port <ce> does not exist in entity" see CASE:893833).

The suggested workaround for now is "generate the FIR with Coregen".

But the audience will probably ask why to spend money for sysgen, if the actual work needs still to be done manually with Coregen. While I can think of some answers, still some skepticism will remain.

Kind regards

  Eilert

[ywu]

I didn't run into this problem when I had 13.1 on my machine. Right now I only have 13.2. I verified that your model works fine in 13.2 with matlab 2010b. Would it be possible for you to upgrade? If that's not an option, can you try explicitly turning on the "ce" port on the FIR block (see the snapshot below) and tying it to a constant 1?

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eilert wrote:

Hi Jim,

thanks fo the hints, I will try them.

Using more DSM48 Macros is no problem for me.

I'm working on some presentation example for HW-Cosimulation, so the design is intended to be big.

Something similar to lab7 of the sysgen Getting Started Guide, just that I need to do it for a ml506 board with a V5 device.

I tried with some smaller FIR to avoid the limitation temporarily, but it seems that the netlister is somewhat broken ("Formal port <ce> does not exist in entity" see CASE:893833).

The suggested workaround for now is "generate the FIR with Coregen".

But the audience will probably ask why to spend money for sysgen, if the actual work needs still to be done manually with Coregen. While I can think of some answers, still some skepticism will remain.

Kind regards

  Eilert

---

[eilert]

Hi Jim,

Thanks for the good news.

Im going to try it.

Also ISE13.2 should be installed soon on our server

Cheers

  Eilert

[eilert]

Hi Jim,

I have tried to explicitly use the ce input as described in your reply.

Unfortunately this approach doesn't work. The same Error as before appears:

HDL simulation model compilation failed.
ERROR:HDLCompiler:1156 - "xlisim_xlfir_compiler_0abc4edd68c25af0536181ef6abbcefe.vhd" Line 1937: Formal port <ce> does not exist in entity <fr_cmplr_v5_0_592eb03683c9104a>. Please compare the definition of block <fr_cmplr_v5_0_592eb03683c9104a> to its component declaration and its instantion to detect the mismatch.
ERROR:HDLCompiler:410 - "xlisim_xlfir_compiler_0abc4edd68c25af0536181ef6abbcefe.vhd" Line 1940: Expression has 25 elements ; expected 24
ERROR:Simulator:777 - Static elaboration of top level VHDL design unit xlisim_xlfir_compiler_0abc4edd68c25af0536181ef6abbcefe in library work failed

Error occurred during "Simulation Initialization".


Reported by:
'fda_fir/FIR Compiler 5.0 '

 Just for comparision. I used the same basic model and script together with a FIR compiler 6.0 (selected ML605 Board as target now) and the simulation works just fine, as one would expect.

So I can at least do some preparation work now and switch to FIR Compiler 5.0 as soon as ISE13.2 is installed on our server.

Kind regards

  Eilert

[ywu · Accepted solution]

Thanks for the update. Can you try one more thing on the model with FIR 5.0 in 13.1: when you open SysGen/Matlab, run "xlCache('clearall')" from the command console, then open your model and run simulation?

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eilert wrote:

Hi Jim,

I have tried to explicitly use the ce input as described in your reply.

Unfortunately this approach doesn't work. The same Error as before appears:

HDL simulation model compilation failed.
ERROR:HDLCompiler:1156 - "xlisim_xlfir_compiler_0abc4edd68c25af0536181ef6abbcefe.vhd" Line 1937: Formal port <ce> does not exist in entity <fr_cmplr_v5_0_592eb03683c9104a>. Please compare the definition of block <fr_cmplr_v5_0_592eb03683c9104a> to its component declaration and its instantion to detect the mismatch.
ERROR:HDLCompiler:410 - "xlisim_xlfir_compiler_0abc4edd68c25af0536181ef6abbcefe.vhd" Line 1940: Expression has 25 elements ; expected 24
ERROR:Simulator:777 - Static elaboration of top level VHDL design unit xlisim_xlfir_compiler_0abc4edd68c25af0536181ef6abbcefe in library work failed

Error occurred during "Simulation Initialization".


Reported by:
'fda_fir/FIR Compiler 5.0 '

 Just for comparision. I used the same basic model and script together with a FIR compiler 6.0 (selected ML605 Board as target now) and the simulation works just fine, as one would expect.

So I can at least do some preparation work now and switch to FIR Compiler 5.0 as soon as ISE13.2 is installed on our server.

Kind regards

  Eilert

---

[eilert]

Hi Jim,

that wuz some good medicine! :-)

It works now. I'm going to put this command in a comment line of my scripts to have it handy when strange things happen.

**UPDATE**

Actually the xlcache('clearall') command was all, that was neccessary.

CE didn't neet to be selected and wired.

Thanks a lot for your help.

Cheers

  Eilert