Digital Signal Processing - IP and Algorithms

[wangxiaoliang]

Hi:

I'm sorry.There is no content in my question.What is that I creat two projects,in which I do the same thing.But now fft4 can work ,while the other cannot.

Where are the problems? The transcripts are in it.

Wish for your help!

[wangxiaoliang]

Hi:

The error messege is this:

# Top level modules:
#  fft_top
# Model Technology ModelSim SE vlog 6.3c Compiler 2007.09 Sep 11 2007
# -- Compiling module glbl
#
# Top level modules:
#  glbl
# vsim -L xilinxcorelib_ver -L unisims_ver -L unimacro_ver -lib work -t 1ps fft_top glbl
# ** Note: (vsim-3812) Design is being optimized...
# ** Error: fft_top.v(61): Module 'myfft' is not defined.
# Optimization failed
# Error loading design
# Error: Error loading design
#        Pausing macro execution
# MACRO ./fft_top.fdo PAUSED at line 7

PLZ HELP

[ticktack · Accepted solution]

It's basically a simulation problem. You didn't compile myfft in the do file. Add "vlog myfft.v" before running vsim command will sovle the problem 

[wangxiaoliang]

Thank you! The problem is solved. But why the problem is in verilog, not in vhdl?

[hussain.elsaid]

excuse me, can anybody tell me why I get zero results from fft when I simulate using ISE simulator. I don't know about verilog very much but I think I did the same in VHDL, however when I tried to simulate your file I got zero results.

please help me ASAP, I am in a bad need to know how this core works please.

[wangxiaoliang]

Hello:

If you have output,that means the core works in a right way,maybe you should check your testbench,and the timing.

[imranqureshi]

Hi,

plz set 500ns time then check!

[imranqureshi]

set 500us simulation time

[deba_techno]

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imranqureshi wrote:
set 500us simulation time

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i have tested the rar fft4 code, with 500us just for experimenting. got "0" result. can u sir, plz fix the problem.