Using Blockram and dedicated multipliers

baesae · ‎03-09-2012

Hey folks

I'm using lots of multipliers and blockram in my project. I read multipliers and blockram share routing ressources, thus the 18 MSB of blockrams data input use the same routing as the dedicated multiplier. Referring to i. e. http://www.xilinx.com/support/answers/20307.htm (citation: Reduce the input width to 18 so that the adjacent block RAM and multiplier can be used) I can use the 18 LSB of block ram inputs simultaneously to a 18 bit multiplier, as long as the block ram stored words <= 18 bits.

So far the theory..

I did have too less ressources for my design, due to the above mentioned reason. I had a few 52 bit and 128 bit block rams. I sliced the their inputs into several 18 bit signals (or less bits). Instead of one 128 bit wide blockram, I'm using eight 16 bit wide blockrams. This should save me some multipliers for my design.

But it doesn't.. Here are the error-messages I received

before my modification (using 128 bit and 52 bit wide block ram):

The design has 30 block-RAM components of which 22 block-RAM components require the adjacent
multiplier site to remain empty.

after the modification (only block rams of width <=18bit)

The design has 58 block-RAM components of which 50 block-RAM components require the adjacent
multiplier site to remain empty.

Instead of using less multiplier sites it used more! How can I teach ISE to use the LSB for the RAM and the MSB for the multiplier, because apparently it does not do so :)

thanks for your help.

baesae

important devices and tool used for this design: Spartan 3 xc3s5000, ISE 13.4, Matlab 2012A

baesae · ‎03-09-2012

I try to express myself differently, maybe somebody feels more motivated to answer then :-)

My device has 104 multipliers and 104 Block RAMs. They share their routing ressources. Thus I cannot use 104 Block RAMs with 36 bits inputs concurrent to the mulitpliers (as the 18 MSB of the blockram are the inputs for the multplier). As can be read in the cited link of my last post it is possible to use both (the multiplier and block ram) when the block ram bit width does not cross 18 bits. My collegue tried this in VHDL directly and it works.

Now, when generating the code from system generator, it seems I cannot use both at one time as the numbers posted in my last post imply.

Has anyone succeeded to share the routing ressources for these two IPs using system generator? Or has anyone a hint what I could do as a workaround?

vlavruhin · ‎12-08-2010

Hi, Baesae.

I tried to recreate your issue using smallest Spartan-3 target xc3s50 and project with two multipliers and three Single Port RAM blocks. Even with 1-bit wide data bus I get following error:

ERROR:Place:665 - The design has 3 block-RAM components of which 3 block-RAM components require the adjacent multiplier site  to remain empty. This is because certain input pins of adjacent block-RAM and multiplier sites share routing ressources. In addition, the design has 2 multiplier components. Therefore, the design would require a total of 5 multiplier sites on the device. The current device has only 4 multiplier sites.

So I guess Answer Record #20307 isn't applicable to this case nowadays.

Can you implement some of your multipliers using logic? Have you tried to check 'Use behavioural HDL' option in Mult block?

Also you can try to tweak generated HDL project in ISE.

Best Regards,
Vitaly.

baesae · ‎03-09-2012

thanks Vitaly! Your answer is very helpful as it shows the problem is recurrent on other systems.

Did you use system generator or did you build the system directly in ISE with coregen and some VHDL-lines? If former applies, here is my suggestion:

We succeeded to implement a design that 'shares' the routing ressources when generating the cores in ISE with core generator without using system generator in earlier projects for spartan 3. Thus I guess the problem is the translation from system generators blockram to vhdl / netlist. It doesn't seem to be fully optimized code.

I'll try now to exchange the blockrams with blackboxes and connect them to blockrams generated by the core-generator. Could you shortly confirm that your design was made in sysgen?

Best regards

baesae

baesae · ‎03-09-2012

I forgot to answer your two questions:

For most multipliers I cannot use logic because of speed reasons. For the multipliers in the FFTs (almost 70): they would use too much space, and speed reason again.

I use the complex multiplier block. I cannot chose the bahavioural HDL option for this block (there's none..?)

vlavruhin · ‎12-08-2010

Yes, Baesae.

Design was made using Single Port RAM and Mult blocks in System Generator 13.4.

baesae wrote:

We succeeded to implement a design that 'shares' the routing ressources when generating the cores in ISE with core generator without using system generator in earlier projects for spartan 3.

What version of ISE was applied? Is it 13.4?

baesae wrote:

I'll try now to exchange the blockrams with blackboxes and connect them to blockrams generated by the core-generator.

Nice idea to check.

Best Regards,
Vitaly.

baesae · ‎03-09-2012

vlavruhin wrote:

What version of ISE was applied? Is it 13.4?

yes, I'm using ISE 13.4. Do you think it might be an issue of ISE 13.4?

What version do you suggest me to take then? 13.2? Thus I'll need to install this version AND change the sysgen-library in matlab, am I right?

I tried with the blackboxes but the try failed: same result as before, no routing ressources were shared :(

vlavruhin · ‎12-08-2010

Hi, Baesae.

baesae wrote:
yes, I'm using ISE 13.4. Do you think it might be an issue of ISE 13.4?

Perhaps. I wonder what version of ISE your collegue have used to implement system with multipliers and BRAMs? Were multipliers generated using CoreGen or written directly in HDL?

What version do you suggest me to take then? 13.2? Thus I'll need to install this version AND change the sysgen-library in matlab, am I right?

Don't know about version. It's just assumption that maybe it works in previous versions. If you are going to try it, then yes, you'll need to change MATLAB version in System Generator setup.

Best Regards,
Vitaly.

baesae · ‎03-09-2012

vlavruhin wrote:

I wonder what version of ISE your collegue have used to implement system with multipliers and BRAMs?

He used ISE 12.2

vlavruhin wrote:

Were multipliers generated using CoreGen or written directly in HDL?

Written in HDL directly

Hmm, the longer this takes the more I'm doubting whether designing with simulink SystGen was the right choice.. :-)

Soon I'm going to try to make a project in HDL for Spartan 3 xc3s50 in ISE with an own-written multiplier to see what happens. Hoping ISE will map it on a dedicated multiplier.. At least I'd see if it works this way then...

vlavruhin · ‎12-08-2010

baesae wrote:

He used ISE 12.2

Is it possible to try to import this project in ISE 13.4?

Written in HDL directly

Are you sure that all this multipliers were implemented as embedded multipliers?

Hmm, the longer this takes the more I'm doubting whether designing with simulink SystGen was the right choice.. :-)

But it's a nice tool for easier and more comfortable design of signal processing systems. :-)

Soon I'm going to try to make a project in HDL for Spartan 3 xc3s50 in ISE with an own-written multiplier to see what happens. Hoping ISE will map it on a dedicated multiplier.. At least I'd see if it works this way then...

Good luck! And please keep this thread updated...

Best Regards,
Vitaly.