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Verifying FFT output between Xilinx CoreGen and Matlab
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05-27-2010 11:36 AM
I am using the Xilinx FFT core v6.0 from ISE 10.1 and I am trying to verify my values with a FFT calculation run on Matlab.
My FFT ISIM simulation runs fine and the simulation values match with the bit accurate model provided by Xilinx. But the order of data is very different from Matlab. My Xilinx FFT block is configured as 4096 pt Pipelined steaming I/O with natural order for floating point values. On Matlab, I use the fft function to determine my values.
For example: This is the result obtained from Xilinx Logicore v6.0 FFT bit accurate model. LHS are the Xilinx values and the Matlab values are on the right. Though the first value matches, everything else differs.
But on closer observation, the 64th value obtained from Xilinx simulation is same as the 2nd value, i.e.
xk_re[64] 6002.34 = Matlab:f2_r[1] 6002.34
So is this behavior expected?? Should there be an additional logic to rearrange the terms??
Xilinx CoreGen FFT real value xk_re
xk_re[0] 117467 Matlab:f2_r[0] 117467
xk_re[1] 1180.82 Matlab:f2_r[1] 6002.34
xk_re[2] 789.918 Matlab:f2_r[2] 126.469
xk_re[3] -548.049 Matlab:f2_r[3] -3516.04
xk_re[4] 3580.31 Matlab:f2_r[4] 1111.52
xk_re[5] -2871.39 Matlab:f2_r[5] 2287.02
xk_re[6] -1346.19 Matlab:f2_r[6] 753.863
xk_re[7] 137.655 Matlab:f2_r[7] 1865.09
xk_re[8] 372.955 Matlab:f2_r[8] 26.8989
xk_re[9] -914.218 Matlab:f2_r[9] -167.196
xk_re[10] -463.463 Matlab:f2_r[10] 788.141
xk_re[11] -875.82 Matlab:f2_r[11] 977.657
xk_re[12] -56.4141 Matlab:f2_r[12] 1087.54
xk_re[13] -544.345 Matlab:f2_r[13] 617.382
xk_re[14] -526.662 Matlab:f2_r[14] 397.022
xk_re[15] -333.39 Matlab:f2_r[15] 181.981
xk_re[16] 216.825 Matlab:f2_r[16] 938
xk_re[17] -1274.68 Matlab:f2_r[17] 237.049
xk_re[18] -521.784 Matlab:f2_r[18] 256.72
xk_re[19] -670.137 Matlab:f2_r[19] 897.621
xk_re[20] -82.1999 Matlab:f2_r[20] 9.97936
xk_re[21] -119.689 Matlab:f2_r[21] 180.858
xk_re[22] -905.393 Matlab:f2_r[22] 1481.65
xk_re[23] -276.808 Matlab:f2_r[23] 557.669
xk_re[24] -219.717 Matlab:f2_r[24] 823.101
xk_re[25] -261.175 Matlab:f2_r[25] 272.421
xk_re[26] -850.324 Matlab:f2_r[26] 552.726
xk_re[27] -263.26 Matlab:f2_r[27] 960.132
xk_re[28] -235.821 Matlab:f2_r[28] 678.96
xk_re[29] 35.2347 Matlab:f2_r[29] 859.29
xk_re[30] -72.7756 Matlab:f2_r[30] 731.413
xk_re[31] -518.872 Matlab:f2_r[31] 378.714
xk_re[32] -249.704 Matlab:f2_r[32] 829
xk_re[33] -296.007 Matlab:f2_r[33] 378.714
xk_re[34] -117.027 Matlab:f2_r[34] 731.413
xk_re[35] -695.503 Matlab:f2_r[35] 859.29
xk_re[36] 172.311 Matlab:f2_r[36] 678.96
xk_re[37] -165.246 Matlab:f2_r[37] 960.132
xk_re[38] -249.19 Matlab:f2_r[38] 552.726
xk_re[39] 42.4766 Matlab:f2_r[39] 272.421
xk_re[40] 229.6 Matlab:f2_r[40] 823.101
xk_re[41] -318.204 Matlab:f2_r[41] 557.669
xk_re[42] 266.831 Matlab:f2_r[42] 1481.65
xk_re[43] -1009.16 Matlab:f2_r[43] 180.858
xk_re[44] -735.485 Matlab:f2_r[44] 9.97936
xk_re[45] -297.726 Matlab:f2_r[45] 897.621
xk_re[46] -294.509 Matlab:f2_r[46] 256.72
xk_re[47] 762.229 Matlab:f2_r[47] 237.049
xk_re[48] 699.253 Matlab:f2_r[48] 938
xk_re[49] -213.069 Matlab:f2_r[49] 181.981
xk_re[50] -413.187 Matlab:f2_r[50] 397.022
xk_re[51] -349.572 Matlab:f2_r[51] 617.382
xk_re[52] -63.1866 Matlab:f2_r[52] 1087.54
xk_re[53] -845.444 Matlab:f2_r[53] 977.657
xk_re[54] -965.319 Matlab:f2_r[54] 788.141
xk_re[55] 70.1314 Matlab:f2_r[55] -167.196
xk_re[56] -157.18 Matlab:f2_r[56] 26.8989
xk_re[57] -646.377 Matlab:f2_r[57] 1865.09
xk_re[58] -2769.69 Matlab:f2_r[58] 753.863
xk_re[59] -2634.43 Matlab:f2_r[59] 2287.02
xk_re[60] -1729.81 Matlab:f2_r[60] 1111.52
xk_re[61] -2057.06 Matlab:f2_r[61] -3516.04
xk_re[62] -5549.6 Matlab:f2_r[62] 126.469
xk_re[63] -3951.05 Matlab:f2_r[63] 6002.34
xk_re[64] 6002.34 Matlab:f2_r[64] 555.219
xk_re[65] 3082.1 Matlab:f2_r[65] 2875
Re: Verifying FFT output between Xilinx CoreGen and Matlab
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06-04-2010 05:45 AM
I tried looking for a pattern and I got
xk_re[0] = 117020.000000 out1[0] = 117020.000000
xk_re[64] = 6299.545898 out1[1] = 6299.546058
xk_re[128] = -480.795319 out1[2] = -480.795307
xk_re[192] = -2098.480957 out1[3] = -2098.480978
xk_re[256] = 514.060181 out1[4] = 514.060169
xk_re[320] = 2333.583740 out1[5] = 2333.583723
xk_re[384] = -1662.341797 out1[6] = -1662.341746
xk_re[448] = 1138.460815 out1[7] = 1138.460846
xk_re[512] = 999.444275 out1[8] = 999.444264
xk_re[576] = 1011.767090 out1[9] = 1011.766937
xk_re[640] = 675.801819 out1[10] = 675.801815
xk_re[704] = -228.494156 out1[11] = -228.494118
xk_re[768] = 125.878403 out1[12] = 125.878388
xk_re[832] = 967.332825 out1[13] = 967.332667
xk_re[896] = 957.770752 out1[14] = 957.770744
xk_re[960] = 521.345032 out1[15] = 521.345267
xk_re[1024] = 517.000000 out1[16] = 517.000000
xk_re[1088] = 304.085236 out1[17] = 304.085171
xk_re[1152] = 8.210644 out1[18] = 8.210658
xk_re[1216] = 977.692871 out1[19] = 977.692783
xk_re[1280] = 939.376404 out1[20] = 939.376446
xk_re[1344] = 834.504822 out1[21] = 834.504807
xk_re[1408] = 509.039398 out1[22] = 509.039446
xk_re[1472] = 687.585693 out1[23] = 687.585502
xk_re[1536] = 214.555710 out1[24] = 214.555736
xk_re[1600] = 266.508942 out1[25] = 266.509008
xk_re[1664] = 35.114548 out1[26] = 35.114484
xk_re[1728] = 328.139496 out1[27] = 328.139565
xk_re[1792] = 460.684998 out1[28] = 460.684997
xk_re[1856] = 881.765320 out1[29] = 881.765423
xk_re[1920] = 741.199890 out1[30] = 741.199907
xk_re[1984] = -33.342484 out1[31] = -33.342660
xk_re[2048] = 494.000000 out1[32] = 494.000000
xk_re[2112] = -33.342667 out1[33] = -33.342660
xk_re[2176] = 741.199890 out1[34] = 741.199907
xk_re[2240] = 881.765503 out1[35] = 881.765423
xk_re[2304] = 460.684998 out1[36] = 460.684997
xk_re[2368] = 328.139587 out1[37] = 328.139565
xk_re[2432] = 35.114426 out1[38] = 35.114484
xk_re[2496] = 266.509064 out1[39] = 266.509008
xk_re[2560] = 214.555710 out1[40] = 214.555736
xk_re[2624] = 687.585388 out1[41] = 687.585502
xk_re[2688] = 509.039368 out1[42] = 509.039446
xk_re[2752] = 834.504761 out1[43] = 834.504807
xk_re[2816] = 939.376404 out1[44] = 939.376446
xk_re[2880] = 977.692810 out1[45] = 977.692783
xk_re[2944] = 8.210655 out1[46] = 8.210658
xk_re[3008] = 304.085205 out1[47] = 304.085171
xk_re[3072] = 517.000000 out1[48] = 517.000000
xk_re[3136] = 521.345215 out1[49] = 521.345267
xk_re[3200] = 957.770813 out1[50] = 957.770744
xk_re[3264] = 967.332397 out1[51] = 967.332667
xk_re[3328] = 125.878403 out1[52] = 125.878388
xk_re[3392] = -228.494202 out1[53] = -228.494118
xk_re[3456] = 675.801880 out1[54] = 675.801815
xk_re[3520] = 1011.766968 out1[55] = 1011.766937
xk_re[3584] = 999.444275 out1[56] = 999.444264
xk_re[3648] = 1138.461060 out1[57] = 1138.460846
xk_re[3712] = -1662.341797 out1[58] = -1662.341746
xk_re[3776] = 2333.583740 out1[59] = 2333.583723
xk_re[3840] = 514.060181 out1[60] = 514.060169
xk_re[3904] = -2098.481201 out1[61] = -2098.480978
xk_re[3968] = -480.795227 out1[62] = -480.795307
xk_re[4032] = 6299.545898 out1[63] = 6299.546058
But why did this happen?? xk_re is the Xilinx bit accurate output and out1 is the Matlab output (using the FFTW3 library)
I did setup the Xilinx FFT core as 4096 pt natural order output with 32 bit floating point. Now I need to reorder the data as per this logic, then do the complex multiplication and then take an IFFT. Now I am not sure if my IFFT values will match Matlab.
Re: Verifying FFT output between Xilinx CoreGen and Matlab
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06-13-2010 08:08 PM
The natural order output of the Xilinx FFT IP will match closely with the Matlab 'fft' function once the effects of scaling are compensated for. If you normalize the output values of the fft results, the only difference should be rounding/quantization errors. There is no need to re-order the output to get the values to match.
I have not used the FFTW3 libary, but in this situation, you may want to try plotting the magnitude of the results of a specific test signal such as an impulse of a few samples. These plots will have an easily identifiable spectrum that will help you to quickly see that the order is correct, and also allow you to identify any potential phase alignment issues.
I would also check that the FFTW3 results and the Matlab 'fft' resuls match, unless you are already confident that this is already the case.
Regards,
Elliot
Re: Verifying FFT output between Xilinx CoreGen and Matlab
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07-01-2010 02:02 PM
The values match between the FFTW3 library and the fft function used in Matlab.
Can you explain some more regd
"If you normalize the output values of the fft results, the only difference should be rounding/quantization errors. There is no need to re-order the output to get the values to match"
Does the normalization function need to be implemented as an additional logic?
Re: Verifying FFT output between Xilinx CoreGen and Matlab
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07-04-2010 06:16 AM
Please take look at this blog http://myfpgablog.blogspot.com/2010/07/fft-results-from-matlab-fft-bit.html with an example showing that the results from from Matlab fft, bit accurate C model and FFT sysgen block match well. Can you attach your script/model/waveform so other people may help find out what's going on?
For FFT, if you select unscaled output for the FFT core or the bit accurate model, the result should match well with Matlab fft() without scaling or normalization.
For IFFT, you will need to scale the output by 1/N in the FFT core or the bit accurate model to match Matlab fft() result. See this blog http://myfpgablog.blogspot.com/2009/11/ifft-in-system-generator.html for additional details.
vivekv wrote:
The values match between the FFTW3 library and the fft function used in Matlab.
Can you explain some more regd
"If you normalize the output values of the fft results, the only difference should be rounding/quantization errors. There is no need to re-order the output to get the values to match"
Does the normalization function need to be implemented as an additional logic?
Jim
Re: Verifying FFT output between Xilinx CoreGen and Matlab
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12-28-2012 10:32 PM
it helps a lot











