Digital Signal Processing - IP and Algorithms

[deltaxlx]

Hello,

I'm currently working with the video scaler IP v6.00.a and I have a problem when generating the core with the GUI interface:

After checking the check box "Include INTC Interface" and generating the core, I don't see any signals corresponding to the INTC_IF interface in the HDL Instantiation Template.

I checked the *.xco file, and the line "CSET has_intc_if=true" seems to be set correctly.

I also tried to instantiate the core with the intc_if signals (even if the instantiate model doesn't include this signals), but I get errors during the synthesis process.

Please tell me how i can access INTC_IF signals in my design.

I'm using the 14.1 version of ISE.

Thank you,

Julien

[bwiec]

Can you provide your .xco so we can test it out?

[deltaxlx]

Here it is:

##############################################################
#
# Xilinx Core Generator version 14.1
# Date: Wed May 23 08:12:36 2012
#
##############################################################
#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
#  Generated from component: xilinx.com:ip:v_scaler:6.00.a
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6vlx75t
SET devicefamily = virtex6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ff784
SET removerpms = false
SET simulationfiles = Structural
SET speedgrade = -1
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Video_Scaler xilinx.com:ip:v_scaler:6.00.a
# END Select
# BEGIN Parameters
CSET aperture_end_line=719
CSET aperture_end_pixel=1279
CSET aperture_start_line=0
CSET aperture_start_pixel=0
CSET auto_hsf=true
CSET auto_vsf=true
CSET chroma_format=4:2:2
CSET coefficient_file=C:\Local\583\DCV6\src\scaler\coe\Example1.coe
CSET component_name=Scaler
CSET has_axi4_lite=true
CSET has_intc_if=true
CSET init_coef_source=COE_File
CSET manual_hsf=1048576
CSET manual_vsf=1048576
CSET maximum_number_of_active_lines_per_input_frame=2048
CSET maximum_number_of_active_lines_per_output_frame=1080
CSET maximum_number_of_active_pixels_per_input_line=2048
CSET maximum_number_of_active_pixels_per_output_line=1920
CSET maximum_number_of_coefficient_sets=1
CSET maximum_number_of_phases=4
CSET number_of_horizontal_phases=4
CSET number_of_horizontal_taps=12
CSET number_of_vertical_phases=4
CSET number_of_vertical_taps=12
CSET output_horizontal_size=1280
CSET output_vertical_size=720
CSET separate_hv_coefs=false
CSET separate_yc_coefs=false
CSET source_horizontal_size=1280
CSET source_vertical_size=720
CSET target_core_clk_freq_mhz=200
CSET target_max_frame_rate=60
CSET video_data_width=10
CSET yc_filter_config=2
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-03-11T15:50:56Z
# END Extra information
GENERATE
# CRC: 1cc178a1

[deltaxlx]

Any information ?

[deltaxlx]

Dear bwiec,

Do you have any news regarding my issue ?

Thank you,

[deltaxlx]

Any workaround please ?