Digital Signal Processing - IP and Algorithms

[m.eragh]

I am using a DDS compiler core in my Project. When I change the option of Keep Hierachy to "No", my design works properly and I get the right DDS Data.

When I change the option to "Yes" , everything is ok in the design except that I get the wrong DDS datas. but surprisingly the Datas are not wrong inherently, every single data is correct but the order of datas has changed. BTW, in this case I get this warning : DDS_tester_ins/DDS_ins/BU2/U0/I_SinCos.i/i_rtl.i_quarter_table.i_addr_reg_c/Mshreg_opt_has_pip.pip is incomplete, the signal does not drive any load pins in the design. 

Could it be the problem? I guess in this case the DDS core is not reading the data from right addresses in its LUT!!!!!!

[bwiec]

Is this hardware or sim?

You will probably need to post your .xco and synthesis reports. Perhaps your instantiation code as well.

Do you have any chipscope/sim plots showing the behavior that you can share?

[m.eragh]

Actually it is the hardware. I have simulated my DDS_Tester module ( instantiation module) and it is working properly. I cannot simulate the whole design simultaneously, since there are some PC interfaces in my design that cannot be simulated.

Anyway, after several tests I came to the point that any change in the deign that removes that warning will lead to the right DDS data. for example I changed the latency of the DDS core and it removed the warning ( I reduced the latency and this is quite awkward that reducing the latency has solved the problem!!!)

 This problem is quite weird since every single data is correct and they follow a logical order!!!!! for example in some of part of the period if we negate that part, it will make a complete Sine Wave but with some samples lost! . As I said before, I guess the DDS core is not reading data from the correct LUT addresses. I cannot post the xco and chipscope waveforms since the project is secured and I don't have permission to move the data :( .

[bwiec]

I would investigate if your design is meeting timing.

What kind of rates are you running at?

[m.eragh]

The timing constraint is not met since I am working with the clock frequencies 24 and 100 Mhz. but the there's only one register between the clock domains( which is just a flag in order to tell the DDS module to start the process). My DDS module is working at 100 Mhz and there's a USB controller module which works at 24 Mhz.The USB controller has a register control to tell the DDS module to start the process.

But in both cases, ( right and wrong DDS data ) the timing constraint is not met . Could it be the problem? Notice that the only clock crossing area is the start flag register.

Another point : I decided to Use two DDS modules : one for phase generating and one for sine data generating in order to see whether phase data order is correct or not. I once used a chipsope core and the DDS datas were correct!!!!!! ( in this case i didnt get that warning).

when I removed the chipscope core, again I got that warning and the wrong data!!

[juergenatduerr]

I am not sure, but can it be the case, that chip socpe registes the data in a correcter/better qay, than you do?

From you description you seem to have a cross domain clocking issue between DDS synthesis and physical observation at USB. (?)

Have you tried to implement an own DDS? Personally I do not use the XI DDS anymore after having compare their output with mine. See the diagram here http://www.mikrocontroller.net/topic/251921#2593000