Digital Signal Processing - IP and Algorithms

[kudos]

sir:

    I am implementing a fir filter in the virtex-4 sx35, and i use the ipcore of fir complier v5.0.  I make the sample frequency is 40MHz and the clock frequency is 200Mhz, and the 3db bandwidth of the filter is 1Mhz. I construct the filter with DA architecture, and the filter type is Single Rate(PDA).  The coefficient width is 16bits and the data width is 14bits , both of which are signed type. The coefficient length is 64. So,the output width is 36(16+14+log(64)). The error i confront is that , in the chipscope i can only view the dout[35:18], and the lower dout[17:0] was not recongnized by chipscope(when i use the "auto create-bus" function in the chipscope, i cannot find the lower 18bits). besides, the control signal "nd","rfd","rdy" also can not be viewed in the chipscope, even though i have take them to the .cdc file before.

what's the possible reason for this question??

the design summary of fir compiler is in the attachments.

Thx

[kudos]

besides, I directly supply the "nd" input of the core with a enable signal of 40MHz.

[chrisar]

It sounds like the signals are either being renameded or optimized out of the design.  You might want to look at your implemenation log to see if these signals are there.

Also if you are not running out of DSP Slices, you might want to just use the MACC structure rather than a DA FIR Structure, which uses only LUTs and FFs.

[kudos]

sir：

    In the implementation log, I find the error as fllow. fir_instance1/instance1 is the instantiation of fir complier v5.0. what's the error mean?