confused about comparting using FP op

juansiahaan · ‎04-16-2012

Hi everyone,

I'm trying to compare incoming signals to a 32-bit floating point. Actually, my incoming signals have only 12-bits by adding the bits one by one in a buffer. I make them to have 32 bits by adding zeroes to the LSBs. However, when I simulated them, none of the results went to "1" (as the FP GUI says that the result will have '1' if the operation is true). Can anyone help me out?

Also, I received warnings about adding the zeroes for the LSB's saying about the constant 0 values...how can I remove them?

Here is the code,

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity comparator_src is
	PORT (CLK : in std_logic;
			RST : in std_logic;
			SDI0 : in std_logic;
			SDI1 : in std_logic;
			SDI2 : in std_logic;
			SDI3 : in std_logic;
			SDI4 : in std_logic;
			SDI5 : in std_logic;
			SDI6 : in std_logic;
			SDI7 : in std_logic;
			trigger0 : out std_logic_vector (0 downto 0) := "0";
			trigger1 : out std_logic_vector (0 downto 0) := "0"; 
			trigger2 : out std_logic_vector (0 downto 0) := "0"; 
			trigger3 : out std_logic_vector (0 downto 0) := "0"; 
			trigger4 : out std_logic_vector (0 downto 0) := "0"; 
			trigger5 : out std_logic_vector (0 downto 0) := "0"; 
			trigger6 : out std_logic_vector (0 downto 0) := "0"; 
			trigger7 : out std_logic_vector (0 downto 0) := "0" 
			);
end comparator_src;

architecture Behavioral of comparator_src is

component compare_FP_IP
	port (
	a: in std_logic_vector(31 downto 0);
	b: in std_logic_vector(31 downto 0);
	clk: in std_logic;
	ce: in std_logic;
	result: out std_logic_vector(0 downto 0));
end component;

signal buffer0 : std_logic_vector (31 downto 0) := (others => '0');
signal buffer1 : std_logic_vector (31 downto 0) := (others => '0');
signal buffer2 : std_logic_vector (31 downto 0) := (others => '0');
signal buffer3 : std_logic_vector (31 downto 0) := (others => '0');
signal buffer4 : std_logic_vector (31 downto 0) := (others => '0');
signal buffer5 : std_logic_vector (31 downto 0) := (others => '0');
signal buffer6 : std_logic_vector (31 downto 0) := (others => '0');
signal buffer7 : std_logic_vector (31 downto 0) := (others => '0');
signal Q0 : std_logic_vector (31 downto 0) := (others => '0');
signal Q1 : std_logic_vector (31 downto 0) := (others => '0');
signal Q2 : std_logic_vector (31 downto 0) := (others => '0');
signal Q3 : std_logic_vector (31 downto 0) := (others => '0');
signal Q4 : std_logic_vector (31 downto 0) := (others => '0');
signal Q5 : std_logic_vector (31 downto 0) := (others => '0');
signal Q6 : std_logic_vector (31 downto 0) := (others => '0');
signal Q7 : std_logic_vector (31 downto 0) := (others => '0');
signal t0 : std_logic_vector (0 downto 0) := "0";
signal t1 : std_logic_vector (0 downto 0) := "0";
signal t2 : std_logic_vector (0 downto 0) := "0";
signal t3 : std_logic_vector (0 downto 0) := "0";
signal t4 : std_logic_vector (0 downto 0) := "0";
signal t5 : std_logic_vector (0 downto 0) := "0";
signal t6 : std_logic_vector (0 downto 0) := "0";
signal t7 : std_logic_vector (0 downto 0) := "0";

constant zeroes : std_logic_vector (19 downto 0) := (others => '0');
signal enable : std_logic := '0';

constant comparator : std_logic_vector (31 downto 0) := "00111101110011001100110011001101";

begin
trigger0 <= t0;
trigger1 <= t1;
trigger2 <= t2;
trigger3 <= t3;
trigger4 <= t4;
trigger5 <= t5;
trigger6 <= t6;
trigger7 <= t7;

compare0 : compare_FP_IP
		port map (
			a => Q0,
			b => comparator,
			clk => CLK,
			ce => enable,
			result => t0);
			
compare1 : compare_FP_IP
		port map (
			a => Q1,
			b => comparator,
			clk => CLK,
			ce => enable,
			result => t1);
			
compare2 : compare_FP_IP
		port map (
			a => Q2,
			b => comparator,
			clk => CLK,
			ce => enable,
			result => t2);
			
compare3 : compare_FP_IP
		port map (
			a => Q3,
			b => comparator,
			clk => CLK,
			ce => enable,
			result => t3);
			
compare4 : compare_FP_IP
		port map (
			a => Q4,
			b => comparator,
			clk => CLK,
			ce => enable,
			result => t4);
			
compare5 : compare_FP_IP
		port map (
			a => Q5,
			b => comparator,
			clk => CLK,
			ce => enable,
			result => t5);
			
compare6 : compare_FP_IP
		port map (
			a => Q6,
			b => comparator,
			clk => CLK,
			ce => enable,
			result => t6);
			
compare7 : compare_FP_IP
		port map (
			a => Q7,
			b => comparator,
			clk => CLK,
			ce => enable,
			result => t7);

	compare : process (CLK)
	variable count : natural range 0 to 36 := 0;
	begin
	if rising_edge (CLK) then
		if RST = '1' then
			buffer0 <= (others => '0');
			buffer1 <= (others => '0');
			buffer2 <= (others => '0');
			buffer3 <= (others => '0');
			buffer4 <= (others => '0');
			buffer5 <= (others => '0');
			buffer6 <= (others => '0');
			buffer7 <= (others => '0');
			enable <= '0';
		else
			buffer0 <= zeroes & buffer0 (10 downto 0) & SDI0;
			buffer1 <= zeroes & buffer1 (10 downto 0) & SDI1;
			buffer2 <= zeroes & buffer2 (10 downto 0) & SDI2;
			buffer3 <= zeroes & buffer3 (10 downto 0) & SDI3;
			buffer4 <= zeroes & buffer4 (10 downto 0) & SDI4;
			buffer5 <= zeroes & buffer5 (10 downto 0) & SDI5;
			buffer6 <= zeroes & buffer6 (10 downto 0) & SDI6;
			buffer7 <= zeroes & buffer7 (10 downto 0) & SDI7;
			if count = 36 then
				count := 0;
				Q0 <= buffer0;
				Q1 <= buffer1;
				Q2 <= buffer2;
				Q3 <= buffer3;
				Q4 <= buffer4;
				Q5 <= buffer5;
				Q6 <= buffer6;
				Q7 <= buffer7;
				enable <= '1';
			else
				count := count + 1;
				enable <= '0';
			end if;
		end if;
	end if;
	end process compare;

end Behavioral;

And the result is in the attachment, I gave stimulation only to my first input...

Regards,

Juan

ywu · ‎11-28-2007

Check the post below:

http://forums.xilinx.com/t5/Digital-Signal-Processing-IP-and/Help-for-real-numbers-to-std-logic-vect...

juansiahaan wrote: