Digital Signal Processing - IP and Algorithms

[avitsur]

hi
i am using the deinterlace IP core and i am read that the deinterlace is connecting to output memory by AXI-MM via the AXI-interconnect IP. the deinterlacer use a a triplet buffer from is side and i want to know if i need to generate in the AXI-interconnect IP with one slve slot for the deinterlace and 3 master slot for the MIG or only 1 master slot and 1 slave slot?

[chrisar]

AXI is a point to point connection.  So depending on how you architect your design, you may not even need the AXI Interconnect.  You may be able to directly connec from MIG to the memory.

If you are sharing the memory, you might want to look at some of the Xilinx App notes that walk through the concept of building a Multi-port memory controller using AXI.

XAPP739 - AXI Multi-Ported Memory Controller

XAPP740 - Designing High-Performance Video Systems with the AXI Interconnect