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AR #34766 - Spartan-6 PLL - Incorrect Compensati on Mode Set
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03-18-2010 08:22 AM
I'm trying to implement a project in EDK 11.4 with the following features:
microblaze
xps_ll_temac
mpmc
interrupt
timer
rs232
i follow xapp 1041 and avnet's (Xilinx Spartan-3A 1800 DSP Starter Board MicroBlaze ll_temac and lwIP Optimized for TCP/IP Performance) tutorial..
i'm facing timing failure...
i recently read the answer:
AR #34766 - Spartan-6 PLL - Incorrect Compensation Mode Set
i would like to ask if the timing failure is due to the PLL syste_synchronous compensation...?
Any ideas about how i can face this timing failure?











