Embedded Development Tools

[rohini.patil]

Hello All,

I have some custome IP cores which uses PLBV46 for communixation with microblaze.Now I want to create an EDK system which uses AXi bus and these custom IP cores.

I checked the documentation in 12.4 wherein I found that AXI to PLB bridge can be used to communicate PLB based IP cores using AXI.

For this there is an interface available in the form of IP core AXI_PLBv46_bridge.

To understand the configuration of this bridge IP core I tried to interface simple UART ip core(PLB based) using this bridge.

I configured the bridge as follows

BEGIN axi_plbv46_bridge
 PARAMETER INSTANCE = axi_plbv46_bridge_0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_INTERCONNECT_S_AXI_MASTERS = microblaze_0.M_AXI_DP
 PARAMETER C_S_AXI_NUM_ADDR_RANGES = 1
 PARAMETER C_S_AXI_RNG1_BASEADDR = 0x84000000
 PARAMETER C_S_AXI_RNG1_HIGHADDR = 0x8400ffff
 PARAMETER C_S_AXI_PROTOCOL = AXI4LITE
 BUS_INTERFACE S_AXI = axi4lite_0
 BUS_INTERFACE MPLB = plb_v46_0
END

still I am not able to test UART with this configuration

Can anyone help me ?

Are there any more configurations required to be done??

Regards,

RP

[dylan]

Can you confirm the clocks of the bridge were connected by looking at the Ports tab in XPS?

Dylan

[rohini.patil]

Hello Dylan, Thank you for the response Please find attached screen shot of the clock port configuration for AXI_PLB_bridge and let me know if there are any wrong settings done

[chrisfisch]

Nearly the same Problem here :)

Someone got an answer?

[nickcake]

hey guys, help!

I'm doing the same try but got "Processor is stalled at address 0x54. UNABLE to STOP MicroBlaze" problems when set the stdio to uartlite which is on the plbv46 bus, then converted by the axi to plb bridge in edk13, to the microblaze M_AXI_DP port. However when I set the stdio to MDM in SDK (bsp standalone setting) and set the run configuration of my hello world elf to connect to JTAG UART, then I'll get the "hello world" printed in the console. ( the first run will give me an error saying ports is not open, but a second run will get it, don't konw why)

so any help? do you guys solve this? thansk in advance!

[nickcake]

the problem is the plb bus clock port is not assigned, this is discovered by creating a fresh design, but for my larger design, edk somehow doesn't give an error for this...