05-22-2012 09:16 AM
Hi I have a big problem with my design.
I want to use a block ram together with the xps bram controller to read and write data to port a of the bram with c-code/microblaze. The next thing is that i have my user logic that reads and writes data to port b.
My blockram should have a data width of 32bit and I want to use 4 brams of my fpga (spartan3e 1600)
First I started to design my user logic in the ise project navigator. To simulate the bram I used the block memory genrator v6.1.
now i have some problems:
1. I can not generate a block ram with the core generator that supports byte write for a spartan 3e fpga to simulate my user logic.
2. In XPS it seems to me that it is not possible to use a block ram without the byte write option.
How can this be?
In XPS it is only possible to generate block ram with the byte write option for the spartan3e but with the ISE coregenerator it is only possible to generate blockram without the bytewrite option. How can I now simulate my userlogic without microblaze???
Shouldn't it be possible to implement a block ram block in the microblaze and use for one port the byte write option and for the other port not?