Embedded Development Tools

[drjohnsmith]

Ta jimwu,

it's always the easy things that are the hardest..

http://www.ultradark.com/07anl02wisdom.htm

[vytautas]

Hello.

I have downloaded your project. Unfortunately, project is created with ISE 11. I’m using 10.1.3, CORDIC version is 4. My version is CORDIC 3. I have used your sqr_tb.vhd file. In attached file you can find some simulation pictures with corresponding test bench files. Signals of data are in hexadecimal format.

2_test.vhd is almost the same as your test bench and 2_diagram.jpeg is corresponding diagram. Please take look at this diagram. Output is changing just 4 times:

IN x0 -> OUT x0

IN x100000 -> OUT x400

IN x80040F -> OUT xB50

IN x4 -> OUT x2

IN x20 -> OUT0 ????

Result by this input (2_test.vhd) is not so bad. But please look at 3_diagram.jpeg and 3_test.vhd. If input value first time is small output is zero always too!

Most interest is 5_diagram.jpeg. This diagram corresponds your send project, but value changes just one time.

Also, I attaché full project (almost the same as your just for version 10).

Please explain what I'm doing wrong?

[drjohnsmith]

Hi

can you not go to ISE 11.x ?

have you regenerate the core from scratch ?

And there is something else strange in your 'pictures', you seem to have different signals between the traces. If it's the same test , with different stimulants, then I'd expect the same traces in all.

I think you had better take big step back, delete the core you have made, make a new one under a new name, and instantiate that into your project. 

Message Edited by drjohnsmith on 05-09-2009 09:40 PM

[ywu · Accepted solution]

Does this AR http://www.xilinx.com/support/answers/32072.htm match what you were seeing?

Cheers,

Jim

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vytautas wrote:

Hello.

I have downloaded your project. Unfortunately, project is created with ISE 11. I’m using 10.1.3, CORDIC version is 4. My version is CORDIC 3. I have used your sqr_tb.vhd file. In attached file you can find some simulation pictures with corresponding test bench files. Signals of data are in hexadecimal format.

2_test.vhd is almost the same as your test bench and 2_diagram.jpeg is corresponding diagram. Please take look at this diagram. Output is changing just 4 times:

IN x0 -> OUT x0

IN x100000 -> OUT x400

IN x80040F -> OUT xB50

IN x4 -> OUT x2

IN x20 -> OUT0 ????

Result by this input (2_test.vhd) is not so bad. But please look at 3_diagram.jpeg and 3_test.vhd. If input value first time is small output is zero always too!

Most interest is 5_diagram.jpeg. This diagram corresponds your send project, but value changes just one time.

Also, I attaché full project (almost the same as your just for version 10).

Please explain what I'm doing wrong?

---

[vytautas]

Thank you for your answer. I don't have any questions now for this topic about!