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05-23-2012 10:05 AM
Thank you very much
05-23-2012 07:53 PM
i have just tried to make a fifo as this tut( http://www.fpgadeveloper.com/2008/10/integrating-vhdl-design-into-peripheral.html) but i choose burst cache line support ,sofware reset and interrupt and tried to use dma to read from this FIFO but it return BUS ERROR. please tell me what i miss?
05-24-2012 05:12 AM
Sorry. i can't see the website?
05-24-2012 07:42 PM
thank every one, i could do it
