Thank you very much
i have just tried to make a fifo as this tut( http://www.fpgadeveloper.com/2008/10/integrating-vhdl-design-into-peripheral.html) but i choose burst cache line support ,sofware reset and interrupt and tried to use dma to read from this FIFO but it return BUS ERROR. please tell me what i miss?
Sorry. i can't see the website?
thank every one, i could do it