09-11-2008 04:58 AM
Processor 400Mhz, Primary PLB DDR/BRAM 100Mhz, Second PLB(OPB old) UART 50Mhz and everything else.
01-20-2009 12:36 PM - edited 01-20-2009 12:37 PM
There are two PLBs in PPC.
I create a system where CPU work on 150Mhz, PLB0 on 100Mhz and PLB1 on 50Mhz(to communicate with slow peripheral, I don't want use OPB).
Is it correct or both PLB bus should work on the same clock?
My second questions is how to define timing constraints? When I make PLB clock higher there is no error/warning during compilation, but system do not work.