04-26-2010 12:13 PM
I am using Xilinx ISE 11.5 to generate a dual port RAM with CoreGen. The RAM is 64kb in size and has a COE file for initial RAM content.
I can import this RAM project as an IP in XPS but the wizard ask which bus interface should be used and it asks for PLB and not MLB. When I skip the interface part, I get an IP which I can't connect to the local memory controllers of the microblaze.
The whole project is generated using the base system wizard and contains a microblaze CPU, 2 local memory controllers (one data, one for instructions) and a dual port RAM. The goal is to replace the default dual port RAM with the one generated by CoreGEN (so I can use the COE or MIF file to initialize the RAM content).
Am I doing it all wrong? Or how do I tell XPS to use the new RAM memory?
Solved! Go to Solution.
05-04-2010 06:39 AM
This question is better handled by the folks over in the EDK/XPS forum. I'll move it over for you.
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05-04-2010 08:05 AM
Are you using this memory for microcontroller instructions or just to hold some nonvolatile data?
Have you looked at XAPP967 as a start? Anyway, You can create a IPIF and instantiate within the userlogic module
your ram. you should choose PLB slave. and you can include every PLB signal related to the slave interface.
This core will require you to include a ngc file in the pcore directory. I think you can add the data to your pcore.
before the coregen creates the ngc file.
05-04-2010 09:25 AM
Cheers for the suggestions but I resorted to modifying the MPD file to make XPS think its a BRAM interface and wrote a wrapper to make everything fit.
Because the VHDL file from CoreGen is only suited for simulation and the RAM content is hardcoded into the NGC file, this approach is not really flexible (each firmware change would require a recompile of the CoreGen project and the moving of all files). As such, I moved on to inferring BRAM from VHDL.