Coregen files in custom Pcore User Logic - Trouble getting complete netlist

simonogg · ‎04-14-2010

Dear all,

We have generated 2 coregen files which sit inside the user_logic portion of a custom pcore unit which is linked into microblaze system. The problem appears that during the generation of the ngc files the 2 coregen files dont get pulled into the top-level pcore netlist.

The structure of the pcore source is:

rbg_2_ycbr (top level pcore wrapper)

plb46_slave_single_i

user_logic

v_rgb2ycrcb_v2_0 (coregen files)

v_ycrcb2rgb_v2_0 (coregen files)

Now the core will go through map & translate fine in ISE so I dont think there is a problem with the syntax or port names as I would think it would fail to build in ISE at this stage.

In XSP it fails with the following:

ERROR:NgdBuild:604 - logical block

   'rgb_2_ycbcr_0/rgb_2_ycbcr_0/USER_LOGIC_I/inst2' with type 'v_ycrcb2rgb_v2_0'
   could not be resolved. A pin name misspelling can cause this, a missing edif
   or ngc file, or the misspelling of a type name. Symbol 'v_ycrcb2rgb_v2_0' is
   not supported in target 'spartan3adsp'.
ERROR:NgdBuild:604 - logical block
   'rgb_2_ycbcr_0/rgb_2_ycbcr_0/USER_LOGIC_I/inst1' with type 'v_rgb2ycrcb_v2_0'
   could not be resolved. A pin name misspelling can cause this, a missing edif
   or ngc file, or the misspelling of a type name. Symbol 'v_rgb2ycrcb_v2_0' is
   not supported in target 'spartan3adsp'.

The coregen files sit in the same directory as the user_logic and pcore top level file and I've added the names to the .PAO file like so before the user_logic and top level lines.

lib rgb_2_ycbcr_v1_00_a v_rgb2ycrcb_v2_0 vhdl
lib rgb_2_ycbcr_v1_00_a v_ycrcb2rgb_v2_0 vhdl

Just to confirm that the 2 instances appear to be missing from the .ngc file we took the XPS generated ngc file for the top level pcore out of the implementation directory and tried to p&r it in ISE and the same error pops up.

It seems to be that XPS is not picking up the 2 corgen files somehow, like I say I dont beleive it to be a misspelling or port mismatch since it compiles in ISE, and the .PAO file appears to be correct so in theory it should pickup those files.

Anyone had similar problems and overcome them? or is there a more detailed report log I can use to see what files are being pulled in during the netlist genersation in XPS?

thanks

Simon

Message Edited by simonogg on 04-14-2010 01:31 AM

pavithra · ‎10-25-2009

hi have u created .ngc file of coregen files. if not create netlist folder in hdl folder present in user defined pheripheral,the store .ngc files in netlist folder . then in .mpd file add following line option style MIX .

tushar_dongre · ‎02-25-2009

Can you please try to delete the instance of your IP from "system assembly view" (instance and external ports).

Rescan the edk project using edk toolbar - "Project" => "Rescan User Repositories".

Then add your IP from "IP Catalog", connect to bus, connect ports, assign address and generate the bitstream.

simonogg · ‎04-14-2010

We got it building now with help from the FAEs at silica. I think it's basically like the 1st reply said:

Move or copy the .ngc files for the 2 coregen components into a new /netlist folder in your pcore device folder (so you will probably have /data, /hdl and /netlist at the same level)

Added/set the following to the .mpd

OPTION RUN_NGCBUILD = TRUE
OPTION STYLE = MIX
OPTION HDL = MIXED

Created a black box .bbd file in /data with the following two lines in it:

FILES
rgb2ycrcb.ngc, ycrcb2rgb.ngc

Not sure if all this is needed, think just the first two things as many things were tinkered with while trying to get it to build.

Thanks

Simon