Embedded Development Tools

[hamid166262]

Hi, I am using XPS 13.3 to create project with PowerPC and a custom IP. I want to debug the custom IP using Chipscope. To do so, I inserted ILA cores into modules of my IP. I tried to define "control" signals of ILA cores as top level signals of my IP and connect them to Chipscope core in XPS. My problem is that the control signals should be bi-directional, but Chipscope core in XPS only can connect to signals with input direction. How should I connect Chipscope signals in XPS to control signals of ILA cores of my IP? Regards, Hamidreza

[johnmcd]

Last time I did this was 13.3. I think the real magic is the definition of the control port in the mpd file. I had the chipscope ICON in my XPS project and my pcore looked something like this:

mpd file:

PARAMETER C_SIMULATION = 0, DT = integer, RANGE = (0:1)
PARAMETER C_VIO_ENABLE = 0, DT = integer, RANGE = (0:1)

PORT vioControl     = "", DIR = IO, VEC = [35:0], THREE_STATE=FALSE, ISVALID = (C_VIO_ENABLE == 1)    

pcore HDL file:

entity traffic_generator is
  generic
  (
    C_SIMULATION    : integer                := 0;
    C_VIO_ENABLE    : integer                := 0
  );
  port
  (
    clk                   : in  std_logic                                ;
    rst                   : in  std_logic                                ;
                                                                         

    -- status/control signals                 
    trafficEn             : in  std_logic                                ;
                                                               
    -- vio interface                                           
    vioControl            : inout std_logic_vector(35 downto 0)     
    
  );
end entity traffic_generator;

  NO_VIO : if C_SIMULATION=1 or C_VIO_ENABLE=0 generate begin
    vioSync  <= (others=>'0');
  end generate NO_VIO;
 
  VIO : if C_SIMULATION=0 and C_VIO_ENABLE=1 generate begin
    -- instantiate chipscope vio core
    trafficGen_vio_I : trafficGen_vio
      port map (
        CLK       => clk_i                   ,   --i        
        CONTROL   => vioControl            ,   --io
        ASYNC_IN  => vioAsync(2 downto 0) ,   --i
        SYNC_OUT  => vioSync(33 downto 0)      --o
      );  
  end generate VIO;

[hamid166262]

John,

I've applied your suggestion, but still no success.

The mpd file is as follows:

BEGIN core

## Generics for VHDL or Parameters for Verilog
PARAMETER CHIPSCOPE = 1, DT = INTEGER
...

PORT rx_frame_ila_control = "", DIR = IO, VEC = [35:0], THREE_STATE=FALSE, ISVALID=(CHIPSCOPE==1)
PORT tx_frame_ila_control = "", DIR = IO, VEC = [35:0], THREE_STATE=FALSE, ISVALID=(CHIPSCOPE==1)

....

and core hdl is like this:

entity core is
  generic
  (
     CHIPSCOPE : integer := 1;

...

)

  port
  (
    rx_frame_ila_control  : inout  std_logic_vector(35 downto 0);
    tx_frame_ila_control  : inout  std_logic_vector(35 downto 0);

    input1           : in std_logic;
    intput2          : in std_logic;
...)
end core;

I want to pass the ila_control signals to inner modules of "core".

In XPS, I've added chipscope_icon module, but when I want to connect its ports to my core (by selecting "core" module from its dropdown list), I could only see "input1" and "input2".

Do you have any other suggestions?

[hamid166262 · Accepted solution]

I found the solution of my problem by more search within xilinx forums:

http://forums.xilinx.com/t5/EDK-and-Platform-Studio/Using-ChipScope-to-look-at-my-custom-IP-core-s-i...

http://www.xilinx.com/support/answers/19423.htm

[johnmcd]

I use a text editor to modify the mhs. Or you could use the 'ports' tab to connect your control signals to the chipscope icon. You would also need to increase the C_NUM_CONTROL_PORTS value on the chipscope icon for the number of control ports you want to access.

The AR you reference is specific to chipscope inserter. That flow also works but you will have to re-insert after every synthesis run.

[hamid166262]

Yes, my problem is the re-insertion procedure :(

I used the "ports" tab and connected the control signals to the chipscope icon, but since I am newbie to chipscope and debugging, I did not know how to use that chipscope icon module :(

Would you please tell me which document should I read to use the chipscope icon which inserted inside the XPS project?

[pritom]

Hamid,

You can have a look at my tutorial, its a very basic guide to use Chipscope in XPS platform. I am quite not sure if that would solve your problem. But let me know your feedback.

Good Luck. 

[hamid166262]

Pritom,

Thanks for the tutorial. I will post the feedback soon.

I think that an advantage of the links I've posted before is that there is no need to synthesize the custopm ip core for tracing its signals and just synthesize after core insertion is needed. Or may be that's its disadvantage! :)

[johnmcd]

Also, using the icon core is quite simple. In XPS, double click on the chipscope icon core, and you will be prompted to add it to your design. Click yes. In the popup window (XPS core config) set the number of control ports to match how many chipscope ILA, VIO, VBA, etc cores you have in your design. This will enable visability of the icon control ports which you then connect to your cores.

[sushantm]

After generating the netlist you can feed the .ngc file into the chipscope,insert the core,generate the new netlist.

Use this updated netlist to generate the bitstream.

when you are done, just open an Chipscope Analyser provide .bit & cdc file.

Monitor the signals.