06-27-2012 10:53 PM
Solved! Go to Solution.
06-28-2012 07:46 PM
Last time I did this was 13.3. I think the real magic is the definition of the control port in the mpd file. I had the chipscope ICON in my XPS project and my pcore looked something like this:
PARAMETER C_SIMULATION = 0, DT = integer, RANGE = (0:1)
PARAMETER C_VIO_ENABLE = 0, DT = integer, RANGE = (0:1)
PORT vioControl = "", DIR = IO, VEC = [35:0], THREE_STATE=FALSE, ISVALID = (C_VIO_ENABLE == 1)
pcore HDL file:
entity traffic_generator is
C_SIMULATION : integer := 0;
C_VIO_ENABLE : integer := 0
clk : in std_logic ;
rst : in std_logic ;
-- status/control signals
trafficEn : in std_logic ;
-- vio interface
vioControl : inout std_logic_vector(35 downto 0)
end entity traffic_generator;
NO_VIO : if C_SIMULATION=1 or C_VIO_ENABLE=0 generate begin
vioSync <= (others=>'0');
end generate NO_VIO;
VIO : if C_SIMULATION=0 and C_VIO_ENABLE=1 generate begin
-- instantiate chipscope vio core
trafficGen_vio_I : trafficGen_vio
port map (
CLK => clk_i , --i
CONTROL => vioControl , --io
ASYNC_IN => vioAsync(2 downto 0) , --i
SYNC_OUT => vioSync(33 downto 0) --o
end generate VIO;
06-29-2012 09:46 PM
I've applied your suggestion, but still no success.
The mpd file is as follows:
## Generics for VHDL or Parameters for Verilog
PARAMETER CHIPSCOPE = 1, DT = INTEGER
PORT rx_frame_ila_control = "", DIR = IO, VEC = [35:0], THREE_STATE=FALSE, ISVALID=(CHIPSCOPE==1)
PORT tx_frame_ila_control = "", DIR = IO, VEC = [35:0], THREE_STATE=FALSE, ISVALID=(CHIPSCOPE==1)
and core hdl is like this:
entity core is
CHIPSCOPE : integer := 1;
rx_frame_ila_control : inout std_logic_vector(35 downto 0);
tx_frame_ila_control : inout std_logic_vector(35 downto 0);
input1 : in std_logic;
intput2 : in std_logic;
I want to pass the ila_control signals to inner modules of "core".
In XPS, I've added chipscope_icon module, but when I want to connect its ports to my core (by selecting "core" module from its dropdown list), I could only see "input1" and "input2".
Do you have any other suggestions?
07-02-2012 08:38 AM
I found the solution of my problem by more search within xilinx forums:
07-02-2012 07:27 PM
I use a text editor to modify the mhs. Or you could use the 'ports' tab to connect your control signals to the chipscope icon. You would also need to increase the C_NUM_CONTROL_PORTS value on the chipscope icon for the number of control ports you want to access.
The AR you reference is specific to chipscope inserter. That flow also works but you will have to re-insert after every synthesis run.
07-02-2012 09:59 PM
Yes, my problem is the re-insertion procedure :(
I used the "ports" tab and connected the control signals to the chipscope icon, but since I am newbie to chipscope and debugging, I did not know how to use that chipscope icon module :(
Would you please tell me which document should I read to use the chipscope icon which inserted inside the XPS project?
07-02-2012 10:06 PM
You can have a look at my tutorial, its a very basic guide to use Chipscope in XPS platform. I am quite not sure if that would solve your problem. But let me know your feedback.
07-03-2012 01:33 AM
Thanks for the tutorial. I will post the feedback soon.
I think that an advantage of the links I've posted before is that there is no need to synthesize the custopm ip core for tracing its signals and just synthesize after core insertion is needed. Or may be that's its disadvantage! :)
07-03-2012 07:15 AM
Also, using the icon core is quite simple. In XPS, double click on the chipscope icon core, and you will be prompted to add it to your design. Click yes. In the popup window (XPS core config) set the number of control ports to match how many chipscope ILA, VIO, VBA, etc cores you have in your design. This will enable visability of the icon control ports which you then connect to your cores.
07-09-2012 01:07 PM
After generating the netlist you can feed the .ngc file into the chipscope,insert the core,generate the new netlist.
Use this updated netlist to generate the bitstream.
when you are done, just open an Chipscope Analyser provide .bit & cdc file.
Monitor the signals.
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