Embedded Development Tools

[masa6614]

Hi,

I'm using XPS 11.2 and trying to enable the cache for the microblaze.  What i did was in configuring the microblaze i set the address range as the same as the OPB Synchronous DRAM (SDRAM) Controller (v1.00e)  as shown:

and then try and build and i get this error:

Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
ERROR:EDK:3193 - issued from TCL procedure "check_icache_fsl" line 172
    microblaze_0 (microblaze) - The ICACHE XCL bus interface is unconnected. The
   MicroBlaze processor (version v5.00.a and higher) requires that the XCL bus
   interface is connected when the ICACHE is enabled. 
ERROR:EDK:440 - platgen failed with errors!
make: *** [implementation/xps_timer_0_wrapper.ngc] Error 2
Done!

 I've looked at some other projects involving enabling cache and I see they are somehow able to connect the microblaze's DXCL and IXCL buses to their memory controller.  Now i know using BSB seems to do it automatically, but how would i do this without using that?

Thanks.

[vsiva]

Please post your MHS file.

From the info below, I suspect that you are using opb_sdram which does not have XCL connections. But I don't know what you've connected your IXCL and DXCL links to.

[masa6614]

Thanks,

attached mhs.

So I wont be able to use the cache because there's no XCL connections?

[vsiva · Accepted solution]

If you look in your MHS, the XCL interfaces are not connected at all. If your intention is to connect it to SDRAM, you have to use a multi ported version of it. e.g. mch_opb_sdram. The mch prefix stands for multi channel, and you need to connect the caches directly to those channels.

For DDR, you can use MPMC.

 BUS_INTERFACE DPLB = mb_plb

 BUS_INTERFACE IPLB = mb_plb

 BUS_INTERFACE DEBUG = microblaze_0_mdm_bus

 BUS_INTERFACE DLMB = dlmb

 BUS_INTERFACE ILMB = il

[masa6614]

Thanks,

well from reading the microblaze reference guide, it seems the caching must go through the XCL buses.  So if I was to continue using the OPB_SDRAM controller, I wouldn't be able to cache the memory of my external SDRAM? I couldnt cache through the OPB bus?

[goran]

Hi,

You can only use cache with XCL.

In order to connect the XCL connections in your design.

Replace opb_sdram with mch_opb_sdram and add this in your .mhs file

On MicroBlaze

 BUS_INTERFACE DXCL = DXCL
 BUS_INTERFACE IXCL = IXCL

On mch_opb_sdram

 BUS_INTERFACE MCH0 = DXCL
 BUS_INTERFACE MCH1 = IXCL

However there might be other parameters that you need to set when moving from opb_sdram to mch_opb_sdram.

The best way is to use BSB for creating a system for a board and then compare the .mhs file with your .mhs file.

Göran

[masa6614]

Thanks alot,

i'll switch to the mch_opb_sdram

[tayeb]

Hi,

I have exactelly the same problem

i followed a tutorial proposed in fpgadeveloper.com to add un IP to PLB (http://www.fpgadeveloper.com/2008/10/create-peripheral-using-peripheral.html )

when I try to generate a bitstream, i have the error below:

ERROR: EDK:3193 - issued from TCL procedure "check_icache_fsl" line 174
    microblaze_0 (microblaze) - The ICACHE XCL bus interface is unconnected. The
   MicroBlaze processor (version v5.00.a and higher) requires that the XCL bus
   interface is connected when the ICACHE is enabled.
Port present in Ethernet_MAC
ERROR:EDK:3371 - Conversion to XML failed.
ERROR:EDK:2569 - Unable to convert MHS into internal data model. Libgen will
   abort.

sorry for my bad english

Thanks

[changemyself]

Hi, I encounted the same problem too, but resolved it luckly.

You should configure the memory which you'd like to settle your Cache in to support XCL bus and then connect it to your processor's XCL bus.

i.e.

  I opened the mpmc IP core configuration gui and in the "Base Configurating" tag I added two XCL buses in PORT1 and PORT2. Then back to the "System Assembly View" and in the port tag, I connected the mpmc's XCL bus to the Microblaze XCL bus. Then finally generat bitstream successfully.(ISE 12.4)

Wish these helpful.