Hello,
I need to write a state machine to control ReadFIFO in user_logic.vhd.
Here is the snippet code which I use:
READ_FIFO_SM_COMB : process(RFIFO2IP_WrAck, read_fifo_cntl_cs, Valid) is
begin
ip2rfifo_wrreq_cmb <= '0';
read_fifo_cntl_ns <= read_fifo_cntl_cs;
case read_fifo_cntl_cs is
when IDLE =>
if (Valid = '1') then
ip2rfifo_wrreq_cmb <= '1';
read_fifo_cntl_ns <= WR_REQ;
end if;
when WR_REQ =>
if (RFIFO2IP_WrAck = '1') then
read_fifo_cntl_ns <= IDLE;
end if;
when others =>
read_fifo_cntl_ns <= IDLE;
end case;
end process READ_FIFO_SM_COMB;
Valid is a signal which tells us that the data are ready and can be written to ReadFIFO (IP2RFIFO_Data are ready).
I also need to generate an interrupt and I decided to use signal RFIFO2IP_WrAck as an interrupt
for the first time (only for debugging). So it looks like:
IP2Bus_IntrEvent(0) <= RFIFO2IP_WrAck;
So it means that when I have a first word in ReadFIFO written IP is generating interrupt to
read from that FIFO with PowerPC. I use device and IP interrupt controlers.
The problem is that in device interrupt controler Transaction Error bit is set. But I can NOT see
why. This bit is generating interrupts continuously so I must clear this bit in service routine. But after
this there is no interrupt being generated.
Does anyone know where is the problem? Is a snippet code wrong? If it's wrong then where? Or
is the problem in signal RFIFO2IP_WrAck which I'm using for generating interrupts?
Please help
Thanks
