Embedded Development Tools

[berufspenner]

Since a few days I can't synthesize my design anymore. Neither with the EDK10.1 SP3 nor with EDK12.1. I get the following error output

<E:/Xilinx/12.1/ISE_DS/EDK/virtex4/data/virtex4.acd> with local file
<E:/Xilinx/12.1/ISE_DS/ISE/virtex4/data/virtex4.acd>
ERROR:Xst:2647 - Failed to run core generator for <trimode_mac_mii_wrapper_fifo_generator_v4_3_1> macro.
ERROR:EDK:546 - Aborting XST flow execution!
INFO:EDK:2246 - Refer to
   C:\MII_MaxSpeed\synthesis\trimode_mac_mii_wrapper_xst.srp for details

Running NGCBUILD ...

Rebuilding cache ...
ERROR:EDK:440 - platgen failed with errors!
make: *** [implementation/trimode_mac_mii_wrapper.ngc] Error 2
Done!

I allready found someting in the answer section but I wouldn't help me so far. I un- and reinstalled it too and took care of enough disk space. But the problem is still there. I installed the EDK12.1 on my notebook where I don't have any problems.

Can someone help me?

[berufspenner]

Unfortunately I need a solution quickly but I didn't found it. Hat vielleicht jemand eine Idee, die das Problem lösen könnte?

[xiaofeip_dup]

Hey,

Post the error message from the synthesis report trimode_mac_mii_wrapper_xst.srp first please.

-Felix

[berufspenner]

Thanks for your reply. I added the whole file as an attachement.

[xiaofeip_dup]

Here's the error message from the report:

Release 12.1 - generatecore $Revision: 1.29.4.1 $ (nt)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
Last:0 Text:Picked up _JAVA_OPTIONS: Xmx768m
Unrecognized option: Xmx768m
Could not create the Java virtual machine.

So the isue is with JVM and possiblly related with the memory allocation.

I'm not sure how to resolve it, but check out AR#20780 first. http://www.xilinx.com/support/answers/20780.htm

-Felix

[berufspenner]

As described I opened the coregen and enlarged the memory from 1024 to 2048 MB but I get the same error again.

[alexsvet]

I ran into the same problem on WinXP SP3 and Xilinx 12.2.

The amount of free RAM is at least 1.5GB when the ISE reports the error.

I tried to change the amount of RAM available for java in Coregen, but that didn't help.

I am pasting the last lines of console output below:

Running XST synthesis ...

INFO:EDK:2502 - The following instances are synthesized with XST. The MPD option
   IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST
   synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized. 
INSTANCE:trimode_mac_mii -
C:\projects\BCM\test\DualPPC405_Ethernet_ddrX\DualPPC4
05_Ethernet_ddrX\DualPPC405_Ethernet_ddrX\DualPPC405_Ethernet_ddrX.mhs line 323
- Running XST synthesis
PMSPEC -- Overriding Xilinx file
<C:/Xilinx/12.2/ISE_DS/EDK/virtex4/data/virtex4.acd> with local file
<C:/Xilinx/12.2/ISE_DS/ISE/virtex4/data/virtex4.acd>
ERROR:Xst:2647 - Failed to run core generator for <trimode_mac_mii_wrapper_fifo_generator_v4_3_1> macro.
ERROR:EDK:546 - Aborting XST flow execution!
INFO:EDK:2246 - Refer to
   C:\projects\BCM\test\DualPPC405_Ethernet_ddrX\DualP
   PC405_Ethernet_ddrX\DualPPC405_Ethernet_ddrX\synthesis\trimode_mac_mii_wrappe
   r_xst.srp for details

Running NGCBUILD ...

Rebuilding cache ...
ERROR:EDK:440 - platgen failed with errors!
make: *** [implementation/trimode_mac_mii_wrapper.ngc] Error 2
ERROR:EDK -  
   Error while running "make -f DualPPC405_Ethernet_ddrX.make netlist".
ERROR: synthesizing XPS module failed!

Process "XPS Process: Synthesize XPS Source" failed

Does somebody has any tips what to check to resolve the problem?

Thanks,

~Aleš

[alexsvet]

I am attaching the *.scr log file.

And below are the relevant details with the error message:

Release 12.2 - generatecore $Revision: 1.29.4.8 $ (nt)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
Last:0 Text:Warning: EDIF Netlist being generated
XSTHandler: XST: HDL Compilation
ERROR: Exception caught when running XST synthesis!
Exception in thread "main" java.lang.RuntimeException: XST has returned an
error: ERROR:HDLCompilers:220 - Open of library file
'../implementation/trimode_mac_mii_wrapper_fifo_generator_v4_3_1_fifo_generator_
v4_3_xst_1_xsd/blk_mem_gen_v2_6/vlg77/ramb36sdp__wrap.bin' failed
    at com.xilinx.sim.base.XSTHandler.implement(Unknown Source)
    at com.xilinx.sim.base.BlackBoxSim.implement(Unknown Source)
    at com.xilinx.xcc.rt.std.Module.addChild(Unknown Source)
    at
com.xilinx.ip.fifo_generator_v4_3.fifo_generator_v4_3$xilinx.implementStructure(
Unknown Source)
    at
com.xilinx.ip.fifo_generator_v4_3.fifo_generator_v4_3.architectureBody(Unknown
Source)
    at com.xilinx.sim.base.HDLSim.implement(Unknown Source)
    at com.xilinx.sim.base.HDLSim.buildStructure(Unknown Source)
    at com.xilinx.sim.base.HDLSim.addHDLSim(Unknown Source)
    at com.xilinx.sim.base.UnnamedHDLSim.doAddHDLSim(Unknown Source)
    at com.xilinx.sim.netlisters.NetlisterAPI.implement(Unknown Source)
    at com.xilinx.sim.netlisters.NetlisterAPI.implement(Unknown Source)
    at com.xilinx.sim.netlisters.NetlisterAPI.process(Unknown Source)
    at com.xilinx.sim.netlisters.NetlisterAPI.netlist(Unknown Source)
    at com.xilinx.sim.netlisters.NetlisterAPI.netlist(Unknown Source)
    at com.xilinx.sim.netlisters.NetlisterAPI.netlist(Unknown Source)
    at com.xilinx.sim.netlisters.NetlisterAPI.main(Unknown Source)

Last:0 Text:(null)
Last:1 Text:(null)
ERROR:encore:132 - Failed to generate unit:
   <trimode_mac_mii_wrapper_fifo_generator_v4_3_1>.

End of process call...
ERROR:Xst:2647 - Failed to run core generator for <trimode_mac_mii_wrapper_fifo_generator_v4_3_1> macro.
-->

Total memory usage is 254232 kilobytes

Number of errors   :    1 (   0 filtered)
Number of warnings :  521 (   0 filtered)
Number of infos    :   20 (   0 filtered)

[mariuszgrad]

Hi,

../implementation/trimode_mac_mii_wrapper_fifo_generator_v4_3_1_fifo_generator_
v4_3_xst_1_xsd/blk_mem_gen_v2_6/vlg77/ramb36sdp__wrap.bin

Do you have that file in your project?

If not than just copy it manually.

Sometimes tools forget about additional files.

I hope this will help.

Best regards, Mariusz.

[alexsvet]

Marius, thanks for reply.

I don't have that file in the project. I also coudn't find it anywhere on the disk.

I guess this compononent has to be syntesized, but the tools fails to do this.

~Aleš