- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic to the Top
- Bookmark
- Subscribe
- Printer Friendly Page
HDL for top level module.
- Mark as New
- Bookmark
- Subscribe
- Subscribe to RSS Feed
- Highlight
- Email to a Friend
- Report Inappropriate Content
10-21-2010 12:24 AM
Hi there,
I am a verilog designer with almost negligeble knowledge in VHDL.
However, when I use the 'Create and import Peripheral' wizard in XPS and I attach my peripheral to PLB, the top level module
always seems to be in VHDL.
Therefore the flexibility is reduced as far as I am concerned.
Could you kindly let me know if there s a way out?
Thank you
Re: HDL for top level module.
- Mark as New
- Bookmark
- Subscribe
- Subscribe to RSS Feed
- Highlight
- Email to a Friend
- Report Inappropriate Content
10-21-2010 08:59 AM
Ask in the EDK forum.
----------------------------------------------------------------
Yes, I do this for a living.
Re: HDL for top level module.
- Mark as New
- Bookmark
- Subscribe
- Subscribe to RSS Feed
- Highlight
- Email to a Friend
- Report Inappropriate Content
10-28-2010 06:03 AM
Hi,
You have an option to use a Verilog "Stub" file. That is the User Logic file will be in verilog. You can place your verilog
code within this file.
The Higher Level file IPIF_YourPeripheralName will be in VHDL. The Higher Level IPIF VHDL file will
use the lower level verilog files.
Gary
There is not much about verilog useage in the XAPP967 App Note. But it might be of some help.











