Embedded Development Tools

[garengllc]

I am trying to get a bare-bones system up and running, but I cannot for the life of me figure out how to make the CLK into the microblaze be single-ended, it always sets it up as differential.  I tried to see if there was any way to tweak it in the Clock Wizard in XPS, but it isn't an option.  Anyone know how to do this (I imagine it is something easy)?  Thanks.

[steve.masson]

Did you try to change the CLK_P and CLK_N in XPS project's MHS file to a single CLK? For exemple:

 PORT CLK = CLK, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000

Also, you might need to replace the _P and _N from your project's UCF constraints file with something like:

NET  CLK                             LOC = E14       |    IOSTANDARD = LVCMOS25;

Then, close everything and re-open / re-generate..

[garengllc]

steve,

My only hesitation is that everytime I make a change in XPS, I will need to make that mod as well since the MHS is autogenerated (because i had considered it).  That was what made me think that there had to be a way to do it via the GUI so the change is persistent, but I haven't found it yet.

[stephenm]

The MHS file isnt auto-generated. If you make changes to the MHS file, and run any of the implementation tools, the MHS file will stay as you left it.

[derekpyoung]

Did you ever figure out how to get a single-ended clock signal into the microblaze component?

I'm trying to do the same thing, using the ML605 dev board and ISE 13.4.  I used XPS to generate the Microblaze components, then edited the .mhs and .ucf files to use a single input.  I used the HDL instantiation template to include the Microblaze core in my top-level VHDL file.  The differential clock pins are run through an ibufds then a gbuf, then into the core.

I can synthesize just fine, but compilation fails during translate with an "ERROR ngdbuild: 604 logical block...".

If I compile by feeding the differential clock input directly into the microblaze core, then I can get through place and route.  But then I don't have access to the 200 MHz clock for the rest of my design.

Derek

[garengllc]

I ended up having to do what Stephen suggested above. I modified the MHS file so that instead of having a differential clock listed, it had a single-ended one.  In the end, it looked like this:

PORT CLK = CLK, DIR = I, SIGIS = CLK, CLK_FREQ = 200000000

That worked fine for me.