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[amego83]

I want to use I2C core in my project , but I do not know how to connect it to the outside pins . Also , I read in the I2C doc that I need I/O bidirectional buffer in my design , how can I add this buffer , Is it already implemented or not ?

I am using virtex 4 FX12 FPGA with power pc processor.

I look forward for your help.

Ahmed,

[tembridis.com]

library UNISIM;
use UNISIM.VComponents.all;
   i_i2c_scl_iobuf : IOBUF
   generic map 
   (
      DRIVE 		=> 12,
      IBUF_DELAY_VALUE 	=> "0",
      IFD_DELAY_VALUE 	=> "AUTO",
      IOSTANDARD 	=> "DEFAULT",
      SLEW 		=> "SLOW"
   )
   port map 
   (
      O 		=> SCL_I_I2C,
      IO		=> SCL_I2C,
      I 		=> SCL_O_I2C,
      T 		=> SCL_T_I2C
   );

   i_i2c_sda_iobuf : IOBUF
   generic map 
   (
      DRIVE 		=> 12,
      IBUF_DELAY_VALUE 	=> "0",
      IFD_DELAY_VALUE 	=> "AUTO",
      IOSTANDARD 	=> "DEFAULT",
      SLEW 		=> "SLOW"
   )
   port map 
   (
      O 		=> SDA_I_I2C,
      IO 		=> SDA_I2C,
      I 		=> SDA_O_I2C,
      T 		=> SDA_T_I2C
   );

Just create two instances of the IOBUFFER macro and connect them like this to your processor core and toplevel ports.

[amego83]

Hallo ,

Thank you for response , but could you tell me how to add this code to my project and where ?

I would be grateful , if you could provide some examples or application notes.

Ahmed ,

[sachingorkhe]

Hi,

One thing can you please let me know. Are you using PPC with EDK suit or just calling PPC instance in your design and synthesis in ISE?

If you are EDK then the flow of instance instantiation is different.

Regards,

Sachin 

[amego83]

I am using EDK only to implement my project. I have virtex 4 FX12 with power PC.

I hope this is the information that you are asking. 

Ahmed ,

[sachingorkhe]

Ahmed,

You need to import XPS IIC from IP catagory window ans drag it to system assembly window into the EDK.

The EDK will automatically attached the IIC to bus. If you want to use XPS IIC which is attached to PLB bus.

You can see the peripherals which are using in your system into the MHS files.

Hope this helps you. If you need anything on the same.

Regards,

Sachin 

[amego83]

Sachin ,

Thanks for your reply , I have done what you suggested ,but in the document of the XPS IIC , It is written "The module expects the design to
include bi-directional I/O buffers which implement open collector drivers for the SDA and SCL signals" , page2, so my question is how to add this buffer to the design.

and how to attach the XPS_IIC SDA and SCL to the external pins of the FPGA ,Is it enough only to modify the UCF constrains file.

Thank in advance .

Ahmed , 

[sachingorkhe]

Ahmed,

What did I understand from your reply is, you want these SCL and SDA pins out of the FPGA..??

If so then you need to just go to the "Ports" window in system assembly and then expand the "xps_iic _0" and then select SCL and SDA pin to external connections. EDK will automatically  added these pins to MHS and UCF. After you done with this changes do generate netlist and bitstream flow for complete synthesis flow.  (Check once if your ucf is reflecting both the pins constraints before synthesis)

Hope this helps you,

Regards,

Sachin 

[amego83]

Sachin ,

I can get form your reply that by doing the steps you have mentioned ,the IIC will be ready to use ,and no need to worry about the I/O bidirectional buffer that is mention in the data sheet of the IIC.

I am confused because of what I have read in the data sheet , please could you have a look in data sheet of the XPS_IIC page 2 .

Ahmed,

[xiaofeip]

Hi Ahmed,

You don't have to worry about the iobufs. It will be handled by XPS automatically. 

-XF