11-25-2009 07:21 AM
I am facing the following problem. I have created a design with four microblaze processor interconnected with fsl and connected with timers and mdm through PLBs. Microblaze 0 and 3 have output throug jtag uart and Microblaze 1 and 2 through RS 232 Uart. All MBs are connected with the debug module. My problem is that I cannot get any output from either one of the microblazes. The design is based on a previous desing with three Microblazes which worked fine. The software platform settings are correct but I still cannot get any output even with the simplest source code, so it has to do with the design and the addition of the forth microblaze. Any ideas what could be wrong? I am attaching the mhs file.
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11-25-2009 07:45 AM
Have you tried with code only executing from LMB?
This would remove any usage of MPMC and external memory.
Can you connect to each MicroBlaze from XMD?
btw, There is no benefit from setting the depth of the FSL to 4, the FIFO will be implemented with SRL16 so the minimum size is 16 (unless you set it to 1).
11-26-2009 01:30 AM
Thank you Goran, you were absolutely right. I was trying to think myself what changes I made in the design since the addition of the forth Microblaze and remembered that the MPMC is no longer connected with the processors through plb, only with XCL. So by executing a program from LMB only it worked. The problem now is that what I really need to do is put all the data in the DDR for execution. By adjusting the linker script and putting the .text portion in the LMB and all the data parts in the DDR again it did not work. How should I modify the linker script for this to work? Or as long as no PLB is connected with the MPMC this is not an option?
11-26-2009 02:06 AM
If you set C_ICACHE_ALWAYS_USED=1 and C_DCACHE_ALWAYS_USED=1 on all MicroBlazes, they will use the XCL connection for all addresses that are within the CACHE_BASEADDR/HIGHADDR even when caches are disabled.
So you don't have to change anything, just enabled these parameters.