07-19-2011 10:21 AM
Good morning all, so I am working on an XPS project in 13.2 with a single AXI MicroBlaze core running completely out of local memory, and a single FSL coprocessor. The FSL coprocessor contains a MIG core, and a test bench. After importing the coprocessor, and making external connections for all the non-FSL pins(everything related to MIG, and the GPIO LEDs) I added LOC constraints to the data/system.ucf file for all of the pins. When I check the pinout report, all the LOC constraints seem to be applied, except two of the GPIO LED constraints are not, and they get mapped to random pins. Any idaes why this might happen? I have LOC'd these pins in previous projects just fine, for some reason the pin is being left empty, and the net is being assigned to a random pin. I attached the UCF, it is messy as it is a MIG UCF file glued onto the end of an XPS UCF file, but it should work.
01-20-2012 02:30 AM
Good morning .... HELP: I have the same problem (GPIO LEDs are mapped in a crazy way) ... I've cleanup the project, I've done a lot of things but nothing happens (today I've upraded to 13.4) .... PLEASE: someone has and idea/solution?
Many many thanks!
01-20-2012 06:44 AM
Same problem here. My work around is to have the EDK system as a submodule in an ISE project and then an additional ucf in ISE in which I duplicate the pin constraint that are iglored in data/system.ucf.
04-20-2012 05:15 PM
I have the same problem. I have created a sample case and submitted to Xilinx.
My workaround so far is to make sure that all pin outputs are driven by unique nets, none of them originating from the same register. Otherwise, it seems they optimize the nets so that a single net is driving multiple IO's. If the IO's are different voltage banks, for instance, one of the IO's get's it's LOC constraint removed, and is randomly assigned.
05-31-2012 02:01 AM
I'm having the same problems. I've got an XPS project that seems fine but when I instantiate it in ISE all the XPS constraints are lost and only the .UCF file in ISE is used - at least for LOC constraints. I then end up with 100+ pins that are unconstrained.....
Anyone got any ideas?
05-31-2012 11:29 AM
What I ended up doing was copying and pasting the UCF constraints from the XPS .ucf file into the ISE .ucf file. I would then use both .ucf files.
I would do this for the pins that were unLOC'd. That seems to do the trick. Then I religiously look at the pin report file at the end of every run, to make sure that no pins are without a LOC. If there is one, I copy it's constraint into the top level ISE .ucf file, and also leave it in the XPI .ucf file. I get some warnings, because the constraints are duplicated into two .ucf files, but I ignore them.
I have repoorted this problem to Xilinx, and they have duplicated the issue, so maybe this issue will be fixed downstream. I am using 13.4.
06-12-2012 03:04 AM
just a few recap thoughts
A) in a pure XPS project the /data directory contains the "MIG.prj" file. This file is the golden file for all pin asignments and will override the UCF i believe for any mig related stuff
B) the system.xmp must point to system.ucf in order for the UCF to be used at all.
C) the implementation/system.bld file should illustrate what conflicts/floaters you have.