Summary:
An interrupt driver program runs on the target, i.e. shows the expected functionality. But in the ISIM simulator, the interrupts
are not coming as expected.
My general question is :what can cause the discrepancy between the correct target functionality and the faulty simulation.
Below are some project details.
#include
"xmk.h"
#include
"os_config.h"
#include
"sys/ksched.h"
#include
"sys/init.h"
#include
"config/config_param.h"
#include
"xparameters.h"
#include
"platform.h"
#include
"platform_config.h"
#include
<pthread.h>
#include
<sys/types.h>
#include
<semaphore.h>
#include
"xaxidma.h"
#include
"xdebug.h"
#include
<sys/intr.h>
#include
"xil_assert.h"
//#include <sys/timer.h>
/************************** Constant Definitions *****************************/
/*
* Device hardware build related constants.
*/
#define
DMA_DEV_ID XPAR_AXIDMA_0_DEVICE_ID
#define
DDR_BASE_ADDR XPAR_V6DDR_0_S_AXI_BASEADDR
#define
MEM_BASE_ADDR (DDR_BASE_ADDR + 0x01000000)
#define
RX_INTR_ID XPAR_INTC_0_AXIDMA_0_S2MM_INTROUT_VEC_ID
#define
TX_INTR_ID XPAR_INTC_0_AXIDMA_0_MM2S_INTROUT_VEC_ID
#define
TX_BUFFER_BASE MEM_BASE_ADDR
#define
RX_BUFFER_BASE (MEM_BASE_ADDR + 0x01000000)
#define
RX_BUFFER_HIGH (MEM_BASE_ADDR + 0x01FFFFFF)
#define
MAX_PKT_LEN 0x10
void
TxIntrHandler(void *Callback);
void
RxIntrHandler(void *Callback);
void
* master_thread1(void *);
void
* master_thread2(void *);
XAxiDma
AxiDma; /* Instance of the XAxiDma */
int
Status;
XAxiDma_Config
*Config;
static
sem_t sem1, sem2;
/* Functions */
int
main()
{
init_platform();
/* Initialize xilkernel */
xilkernel_init();
int_id_t id1 = XPAR_MICROBLAZE_0_INTC_ETHERNET_DMA_MM2S_INTROUT_I
int_id_t id2 = XPAR_MICROBLAZE_0_INTC_ETHERNET_DMA_S2MM_INTROUT_I
register_int_handler(id1, TxIntrHandler, NULL);
register_int_handler(id2, RxIntrHandler, NULL);
enable_interrupt(id1);
enable_interrupt(id2);
Config = XAxiDma_LookupConfig(DMA_DEV_ID);
// Initialize DMA engine
if (XST_SUCCESS != XAxiDma_CfgInitialize(&AxiDma, Config)){
return 0;
}
/* Disable all interrupts before setup */
XAxiDma_IntrDisable(&AxiDma, XAXIDMA_IRQ_ALL_MASK,
XAXIDMA_DMA_TO_DEVICE);
XAxiDma_IntrDisable(&AxiDma, XAXIDMA_IRQ_ALL_MASK,
XAXIDMA_DEVICE_TO_DMA);
/* Enable all interrupts */
XAxiDma_IntrEnable(&AxiDma, XAXIDMA_IRQ_ALL_MASK,
XAXIDMA_DMA_TO_DEVICE);
XAxiDma_IntrEnable(&AxiDma, XAXIDMA_IRQ_ALL_MASK,
XAXIDMA_DEVICE_TO_DMA);
sem_init(&sem1, 1, 0);
sem_init(&sem2, 1, 0);
/* Create the master thread */
xmk_add_static_thread(master_thread1, 0);
xmk_add_static_thread(master_thread2, 0);
/* Start the kernel */
xilkernel_start();
disable_interrupt(id1);
disable_interrupt(id2);
/* Never reached */
cleanup_platform();
return 0;
}
/* The master thread */
void
* master_thread1(void *arg)
{
u8 *TxBufferPtr;
u8 Value;
unsignedint x;
unsignedint y;
TxBufferPtr = (
u8 *)TX_BUFFER_BASE ;
Value = 0x0;
y = 0;
while(1){
for(x = 0; x < 50; x++){
for(y = 0; y < 20; y++){
TxBufferPtr[y] = Value;
Value = (Value + 1) & 0xFF;
}
Status = XAxiDma_SimpleTransfer(&AxiDma,(
u32) TxBufferPtr,
MAX_PKT_LEN, XAXIDMA_DMA_TO_DEVICE);
sem_wait(&sem1);
}
}
}
void
* master_thread2(void *arg)
{
u8 *RxBufferPtr;
RxBufferPtr = (
u8 *)RX_BUFFER_BASE;
while(1){
Status = XAxiDma_SimpleTransfer(&AxiDma,(
u32) RxBufferPtr,
MAX_PKT_LEN, XAXIDMA_DEVICE_TO_DMA);
sem_wait(&sem2);
}
}
void
TxIntrHandler(void *Callback)
{
u32 IrqStatus;
/* Read pending interrupts */
IrqStatus = XAxiDma_IntrGetIrq(&AxiDma, XAXIDMA_DMA_TO_DEVICE);
/* Acknowledge pending interrupts */
XAxiDma_IntrAckIrq(&AxiDma, IrqStatus, XAXIDMA_DMA_TO_DEVICE);
if ((IrqStatus & XAXIDMA_IRQ_IOC_MASK)) {
sem_post(&sem1);
}
}
void
RxIntrHandler(void *Callback)
{
u32 IrqStatus;
/* Read pending interrupts */
IrqStatus = XAxiDma_IntrGetIrq(&AxiDma, XAXIDMA_DEVICE_TO_DMA);
/* Acknowledge pending interrupts */
XAxiDma_IntrAckIrq(&AxiDma, IrqStatus, XAXIDMA_DEVICE_TO_DMA);
if ((IrqStatus & XAXIDMA_IRQ_IOC_MASK)) {
sem_post(&sem2);
}
}
