Embedded Development Tools

[kosmovirus]

Hello there. So... for a couple of days now (I’m not telling how many) I’ve started hating the internet. I've been searching for a simple and quick tutorial on self-reconfiguration on a FPGA board (clearly). So far, from what I’ve been reading and stumbling upon, I have to use the ICAP module/primitive to synthesize the partial bit streams. From what I gathered the partial bit streams could be stored in BRAMs (Block RAM).

I’ve read all the documents that I’ve found on that matter and sincerely I didn’t understand it all. I’m sort of a beginner on the self/partial reconfiguration topic and I literally have no one to ask on this matter so I was hoping to find some help here (please please please).

 I’ve drawn a simple hardware design so you can understand how basic is the information I that I need. So … I have a simple module that keeps a board LED lit. This is the module that I need to reconfigure with the help of a button so that the resulted configuration will shut down the LED. 

OK... now here are the questions and requests:

• How can I write a bit file/stream into a BRAM? 
• How can a read from a BRAM?
• Is it enough, once I have read a bit stream from a BRAM, to just send it to ICAP so that the reconfiguration would occur?
• How should i send the bit stream to ICAP? How can i interface it with the BRAM Reader?
• Is this the simplest solution? (I’ve seen that the BRAM Reader could be replaced with a PicoBlaze… any information on that? I have worked with PicoBlaze before so that would be helpful)
• Can I find a simple coded example (like this one) on this matter (or at least a tutorial)?
• If you could provide me with any kind of code on any part of the design  OH GOD PLEASE DO. (I’m a Verilog cruncher so I’m not good at VHDL… but I could manage)

I would really appreciate any kind of help. The board I’m working on has a Virtex 5, I don’t know specific details because I don’t have it right now with me, but if that information is necessary I will provide it. The project that I’m working on is a fairly complex one, but I really need these basics so I can start properly.

Finally I beg of you to help me as quick as you can.

Thanks !!

[kosmovirus]

Please someone help!!

[chenweit]

Hi,

V5 BRAM allows you to store 32K bits. A config frame for V5 is 1312 bits. That means, you get to store 24 frames per BRAM. Just to give you an Idea, a single column of CLB that spans one clock region (minimum unit for PR) requires 36 frames. Practically, for this application to work, your PR region and variation modules must be rather controlled.

ICAP is just like SMAP interface. Please refer to configuration user guide for more information.

http://www.xilinx.com/support/documentation/virtex-5_user_guides.htm

Do remember to set ICAP WIDTH correct and account for how config expects the data (in term of MSB, noted in config UG).

You may want to consider posting PR related questions in the hierarchical design forum. You FAE can assist in system concept and Xilinx tech support for general implementation inquiry.

Regards,

Wei