Hi all, I keep reading that the Microblaze will run upwards of 210MHz on a V5. I have the ML506 board (with a -1 grade V5SX) and the BSB will never allow anything over 125MHz in the wizard. Is it just a simple matter of tweaking the input clock after the wizard finishes up its magic? Or is there more to it? For the record, I just want to bump it up to 133MHz to run synchronously with my DDR2 MPMC. Cheers, Sean
The limiting factor is typically going to be the bus. In the previous topology, the max speed of the opb bus was typically 100 MHz virtex devices and even less in spartan devices. I am not done too much experimenting with the speed of the new PLB v.46 bus in 9.2i, but this will probably also be your limiting factor. BSB is typically conservative when creating designs such that is not going to push the envelope in terms of speed and performace. However, you can modify the clocks, run the design the design thorugh the tools, and verify the timing of the design.
Speed grade was one of my initial concerns, but even if I specified the fastest grade, BSB still only gave options up to 125MHz.
I'm regenerating it with the clock bumped. Shouldn't be a problem I
don't think, as ISE is always reporting I have plenty of headroom in
the design. Was just curious if there was an option I was missing
somewhere.
