Embedded Development Tools

[bouvett]

By the way I must add that I am using the Nexys2 board with 1200K Gates. Software version 13.4.

Thanks again

[rytlig]

Did you solve your problem bouvett?

I seem to have the same problem using EDK and SDK 13.4. I have older bitfiles that work fine, but since yesterday I have not been able to produce good bitfiles for my Spartan6 board. I did not change anything outside a small user core I have and there are no obvious routing errors etc.

Wen I run "connect mb mdm" I get:

JTAG chain configuration
--------------------------------------------------
Device ID Code IR Length Part Name
1 0402e093 6 XC6SLX75T
ERROR: Could not detect MDM peripheral on hardware. Please check:
1. If FPGA is configured correctly
2. MDM Core is instantiated in the design

When I try to launch my software using the newer bitfiles I get this error message:

Any suggestions as to what I can try is welcome.

thanks,

Andreas

[stephenm]

Hello Andreas,

Can you try the suggestion in the attached pdf?

[g.glowacki@wasko.pl]

For people how also experience this problem: Please check if You have properly configured clock in EDK, frequency, ports and even if it's connected to the device. It took me 4 days to get that i had wrong clock configured.

[rytlig]

I solved my problem by deleting the last added core in EDK, then I did a compile and it worked. After that I added the core again in the excact same way, and now everything worked. I have seen this issue twice now, with 2 different cores and this solution worked both times.

Btw. I am using 13.4.

[garengllc]

I've had the same problems as well.  Seems to happen after I make a change to the Verilog and re-synthesize.  The SDK knows about the new .bit files, but seems to get hung somehow and I am not sure how I fixed it previously, but nothign methodical seems to work (unplugging the USB JTAG, power cycling the board, closing/opening SDK, etc.).  I too am using 13.4.

[gh_kei]

I had posted about this problem yesterday, and that posting got removed.

In version 13.4, the "cse" value for the Virtex-6 is wrong in idcode.lst.  Watching the XMD console while programming reveals this error.

The default location for the file is: $XILINX/ISE_DS/ISE/data/cse/idcode.lst

Hope that helps.

GH

[garengllc]

Any chance you could elaborate on that some?  I am unfortuantly missing what your are driving at.  Thanks!

[gh_kei]

That made the problem go away ONCE. The 2nd time I tried, it was right back.

[garengllc]

I still seem to be having these issues after changing the ISE project.  Then when I got to the SDK to re-compile, and download everything seems fine; but when I click on debug I get the errors.  Now I will have these errors for a while while I try to figure it out, and eventually they will go away, but I am nto sure why or how...  It kills productivity for a bit and makes me hesitant to make changes in ISE out of fear of this happening.