Embedded Development Tools

[314314314]

I was trying to make a custom PLBv46 peripheral and add it to the microblaze based system.

The custom peripheral contains 2 Coregen generated components, a BRAM and a DCM.

What I did:

1. Create a XPS system with BSB wizard

2. Create a custom peripheral with "Create and import peripheral wizard",

     together with the automatically generated ISE & XST project files.

3. Goto the automatically generated ISE project and modify the user_logic.vhdl

4. Add a DCM module in the ISE project (using the core generator) and instantiate the DCM in the user_logic.vhdl.

5. Add a block ram module in the ISE project (using the core generator) and instantiate the BRAM in the user_logic.vhdl.

6. save the ISE project.

7. Go back to XPS, add the peripheral to the system, set connection and addresses.

8. press button "Generate bitstream".

9. Get error message during ngdbuild

=====================Console Message======================

..........Omitting many lines..........

Processing BMM file "system.bmm" ...

Checking expanded design ...

WARNING:NgdBuild:443 - SFF primitive

'microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Decode_I/Using_FPGA.
Gen_Bits[27].MEM_EX_Result_Inst' has unconnected output pin

ERROR:NgdBuild:604 - logical block

'hash_module_0/hash_module_0/USER_LOGIC_I/DCMx4' with type 'DCMtest' could
not be resolved. A pin name misspelling can cause this, a missing edif or ngc
file, case mismatch between the block name and the edif or ngc file name, or
the misspelling of a type name. Symbol 'DCMtest' is not supported in target
'spartan6'.

WARNING:NgdBuild:478 - clock net mdm_0/bscan_drck1 with clock driver
mdm_0/mdm_0/BUFG_DRCK1 drives no clock pins

Partition Implementation Status
-------------------------------

No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
Number of errors: 1
Number of warnings: 3

Total REAL time to NGDBUILD completion: 1 min 26 sec
Total CPU time to NGDBUILD completion: 1 min 25 sec

One or more errors were found during NGDBUILD. No NGD file will be written.

Writing NGDBUILD log file "system.bld"...
ERROR:Xflow - Program ngdbuild returned error code 2. Aborting flow execution...
make: *** [__xps/system_routed] Error 1
Done!

====================End of console message======================

What I observed,

1. If I implement the custom peripheral using ISE, I won't get error with ngdbuild.

2. I realize that DCM ipcore doesn't come along with a .ngc file.

I have been working on this problem for whole day.........Please give me some clues........

Many thanks,

Newbie

[austin]

N,

Doesn't coregen create the instaiations for the DCM and BRAM?  Why did you need to do it again?  Perhaps it is complaining that is has a DCM and a BRAM that it doesn't know what to do with (or the higher level is so confused)?

[314314314]

Hi Austin,

For the instantiation of DCM and BRAM, I followed the guidelines in the "HDL instantiation template" and copied the template codes into user_logic.vhdl.

=============The following code was copied to  user_logic architecture header============
component DCMtest
port
(
CLK_IN1 : in std_logic;
CLK_OUT1 : out std_logic;
RESET : in std_logic;
LOCKED : out std_logic
);
end component;

=================The following code was copied to the user_logic architecture==================

myDCM : DCMtest
port map
(
CLK_IN1 => Bus2IP_Clk,
CLK_OUT1 => myClk,
RESET => Bus2IP_Reset,
LOCKED => myLocked);

================================End ==============================

Are you saying that the above steps were unnecessary and caused the error?

Thanks.

[hgleamon1]

I am a bit confused as to what you are trying to achieve.

When you developed your embedded system using BSB in XPS, surely that included a "clock_generator" block? Do you really *need* to try and instantiate another DCM in your system? May be you do but I'm just asking.

Moving on from that, what files does coregen produce for the DCM? Can/have you included the relevant output file into your ISE project (i.e. does ISE "know" where to find the description of your DCM)?

Lastly, you could avoid coregen completely and instantiate the DCM primitive (relevant to your device) instead. Just be sure to include the Xilinx primitive library in your user_logic if you do that.

Regards,

Howard

[golson]

Maybe you are missing the underlying code beneath your component declaration.

A few years ago I instantiated a DCM in a pcore to create a 40 mhz clock.  Today I now would just add a clock output

to the Clock generator.

[ahmad_seyfi]

Hi,

When you make change in the generated ipCore which is generated by XPS (using ISE) and the change includes adding vhdl files or adding some ports, it is necessary to import the ipCore as existing ip. In this way, XPS generates new *.pao file that includes information about your additional vhdl files. Then you can add the ipCore to your project, clean all generated files and update bitstream.