Embedded Development Tools

[spilgeo]

Hi,

I use EDK 13.4 and I want to use the xapp433.pdf to make the web server. But I have many problems as u can see in the picture. My mhs file is shown down. has somebody any idea?Does anybody try it to do this in Spartan 6?

I follow the xapp433.pdf exactly but i have these errors.

# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 13.4 Build EDK_O.87xd
# Thu May 17 11:04:26 2012
# Target Board: Digilent Nexys 3 Board Rev B
# Family: spartan6
# Device: xc6slx16
# Package: csg324
# Speed Grade: -3
# Processor number: 1
# Processor 1: microblaze_0
# System clock frequency: 66.7
# Debug Interface: On-Chip HW Debug Module
# ##############################################################################
PARAMETER VERSION = 2.1.0

PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX_pin, DIR = I
PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX_pin, DIR = O
PORT fpga_0_DIP_Switches_8Bits_GPIO_IO_I_pin = fpga_0_DIP_Switches_8Bits_GPIO_IO_I_pin, DIR = I, VEC = [0:7]
PORT fpga_0_LEDs_8Bits_GPIO_IO_O_pin = fpga_0_LEDs_8Bits_GPIO_IO_O_pin, DIR = O, VEC = [0:7]
PORT fpga_0_Push_Buttons_4Bits_GPIO_IO_I_pin = fpga_0_Push_Buttons_4Bits_GPIO_IO_I_pin, DIR = I, VEC = [0:3]
PORT fpga_0_Ethernet_Lite_PHY_tx_clk_pin = fpga_0_Ethernet_Lite_PHY_tx_clk_pin, DIR = I
PORT fpga_0_Ethernet_Lite_PHY_rx_clk_pin = fpga_0_Ethernet_Lite_PHY_rx_clk_pin, DIR = I
PORT fpga_0_Ethernet_Lite_PHY_crs_pin = fpga_0_Ethernet_Lite_PHY_crs_pin, DIR = I
PORT fpga_0_Ethernet_Lite_PHY_dv_pin = fpga_0_Ethernet_Lite_PHY_dv_pin, DIR = I
PORT fpga_0_Ethernet_Lite_PHY_rx_data_pin = fpga_0_Ethernet_Lite_PHY_rx_data_pin, DIR = I, VEC = [3:0]
PORT fpga_0_Ethernet_Lite_PHY_col_pin = fpga_0_Ethernet_Lite_PHY_col_pin, DIR = I
PORT fpga_0_Ethernet_Lite_PHY_rx_er_pin = fpga_0_Ethernet_Lite_PHY_rx_er_pin, DIR = I
PORT fpga_0_Ethernet_Lite_PHY_rst_n_pin = fpga_0_Ethernet_Lite_PHY_rst_n_pin, DIR = O
PORT fpga_0_Ethernet_Lite_PHY_tx_en_pin = fpga_0_Ethernet_Lite_PHY_tx_en_pin, DIR = O
PORT fpga_0_Ethernet_Lite_PHY_tx_data_pin = fpga_0_Ethernet_Lite_PHY_tx_data_pin, DIR = O, VEC = [3:0]
PORT fpga_0_Ethernet_Lite_PHY_MDC_pin = fpga_0_Ethernet_Lite_PHY_MDC_pin, DIR = O
PORT fpga_0_Ethernet_Lite_PHY_MDIO_pin = fpga_0_Ethernet_Lite_PHY_MDIO_pin, DIR = IO
PORT fpga_0_PS2_Mouse_Keyboard_PS2_1_DATA_pin = fpga_0_PS2_Mouse_Keyboard_PS2_1_DATA_pin, DIR = IO
PORT fpga_0_PS2_Mouse_Keyboard_PS2_1_CLK_pin = fpga_0_PS2_Mouse_Keyboard_PS2_1_CLK_pin, DIR = IO
PORT fpga_0_PS2_Mouse_Keyboard_PS2_2_DATA_pin = fpga_0_PS2_Mouse_Keyboard_PS2_2_DATA_pin, DIR = IO
PORT fpga_0_PS2_Mouse_Keyboard_PS2_2_CLK_pin = fpga_0_PS2_Mouse_Keyboard_PS2_2_CLK_pin, DIR = IO
PORT fpga_0_Digilent_Usb_Epp_IFCLK_pin = fpga_0_Digilent_Usb_Epp_IFCLK_pin, DIR = I
PORT fpga_0_Digilent_Usb_Epp_STMEN_pin = fpga_0_Digilent_Usb_Epp_STMEN_pin, DIR = I
PORT fpga_0_Digilent_Usb_Epp_FLAGA_pin = fpga_0_Digilent_Usb_Epp_FLAGA_pin, DIR = I
PORT fpga_0_Digilent_Usb_Epp_FLAGB_pin = fpga_0_Digilent_Usb_Epp_FLAGB_pin, DIR = I
PORT fpga_0_Digilent_Usb_Epp_FLAGC_pin = fpga_0_Digilent_Usb_Epp_FLAGC_pin, DIR = I
PORT fpga_0_Digilent_Usb_Epp_SLRD_pin = fpga_0_Digilent_Usb_Epp_SLRD_pin, DIR = O
PORT fpga_0_Digilent_Usb_Epp_SLWR_pin = fpga_0_Digilent_Usb_Epp_SLWR_pin, DIR = O
PORT fpga_0_Digilent_Usb_Epp_SLOE_pin = fpga_0_Digilent_Usb_Epp_SLOE_pin, DIR = O
PORT fpga_0_Digilent_Usb_Epp_FIFOADR_pin = fpga_0_Digilent_Usb_Epp_FIFOADR_pin, DIR = O, VEC = [1:0]
PORT fpga_0_Digilent_Usb_Epp_PKTEND_pin = fpga_0_Digilent_Usb_Epp_PKTEND_pin, DIR = O
PORT fpga_0_Digilent_Usb_Epp_EPPRST_pin = fpga_0_Digilent_Usb_Epp_EPPRST_pin, DIR = I
PORT fpga_0_Digilent_Usb_Epp_DB_pin = fpga_0_Digilent_Usb_Epp_DB_pin, DIR = IO, VEC = [7:0]
PORT fpga_0_mem_bus_mux_0_MEM_ADDR_pin = fpga_0_mem_bus_mux_0_MEM_ADDR_pin, DIR = O, VEC = [0:22]
PORT fpga_0_mem_bus_mux_0_DQ_pin = fpga_0_mem_bus_mux_0_DQ_pin, DIR = IO, VEC = [0:15]
PORT fpga_0_mem_bus_mux_0_MEM_OEN_pin = fpga_0_mem_bus_mux_0_MEM_OEN_pin, DIR = O
PORT fpga_0_mem_bus_mux_0_MEM_WEN_pin = fpga_0_mem_bus_mux_0_MEM_WEN_pin, DIR = O
PORT fpga_0_mem_bus_mux_0_RAM_CEN_O_pin = fpga_0_mem_bus_mux_0_RAM_CEN_O_pin, DIR = O
PORT fpga_0_mem_bus_mux_0_RAM_BEN_O_pin = fpga_0_mem_bus_mux_0_RAM_BEN_O_pin, DIR = O, VEC = [0:1]
PORT fpga_0_mem_bus_mux_0_FLASH_ADDR_pin = fpga_0_mem_bus_mux_0_FLASH_ADDR_pin, DIR = O, VEC = [5:7]
PORT fpga_0_mem_bus_mux_0_FLASH_CEN_O_pin = fpga_0_mem_bus_mux_0_FLASH_CEN_O_pin, DIR = O
PORT fpga_0_mem_bus_mux_0_FLASH_RPN_O_pin = fpga_0_mem_bus_mux_0_FLASH_RPN_O_pin, DIR = O
PORT fpga_0_mem_bus_mux_0_QUAD_SPI_C_O_pin = fpga_0_mem_bus_mux_0_QUAD_SPI_C_O_pin, DIR = O
PORT fpga_0_mem_bus_mux_0_QUAD_SPI_S_O_pin = fpga_0_mem_bus_mux_0_QUAD_SPI_S_O_pin, DIR = O
PORT fpga_0_mem_bus_mux_0_MOSI_QUAD_SPI_pin = fpga_0_mem_bus_mux_0_MOSI_QUAD_SPI_pin, DIR = IO
PORT fpga_0_clk_1_sys_clk_pin = CLK_S, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1

BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER C_USE_BARREL = 1
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER HW_VER = 8.20.b
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
BUS_INTERFACE DPLB = mb_plb
BUS_INTERFACE IPLB = mb_plb
BUS_INTERFACE DEBUG = microblaze_0_mdm_bus
PORT MB_RESET = mb_reset
PORT INTERRUPT = microblaze_0_Interrupt
END

BEGIN plb_v46
PARAMETER INSTANCE = mb_plb
PARAMETER HW_VER = 1.05.a
PORT PLB_Clk = clk_66_6667MHz
PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 2.00.b
PORT LMB_Clk = clk_66_6667MHz
PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
PARAMETER INSTANCE = dlmb
PARAMETER HW_VER = 2.00.b
PORT LMB_Clk = clk_66_6667MHz
PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 3.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00003fff
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_port
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 3.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00003fff
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = ilmb_port
END

BEGIN bram_block
PARAMETER INSTANCE = lmb_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port
BUS_INTERFACE PORTB = dlmb_port
END

BEGIN xps_uartlite
PARAMETER INSTANCE = RS232_Uart_1
PARAMETER C_BAUDRATE = 9600
PARAMETER C_DATA_BITS = 8
PARAMETER C_USE_PARITY = 0
PARAMETER C_ODD_PARITY = 0
PARAMETER HW_VER = 1.02.a
PARAMETER C_BASEADDR = 0x84000000
PARAMETER C_HIGHADDR = 0x8400ffff
BUS_INTERFACE SPLB = mb_plb
PORT RX = fpga_0_RS232_Uart_1_RX_pin
PORT TX = fpga_0_RS232_Uart_1_TX_pin
PORT Interrupt = RS232_Uart_1_Interrupt
END

BEGIN xps_gpio
PARAMETER INSTANCE = DIP_Switches_8Bits
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_GPIO_WIDTH = 8
PARAMETER C_INTERRUPT_PRESENT = 0
PARAMETER C_IS_DUAL = 0
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0x81440000
PARAMETER C_HIGHADDR = 0x8144ffff
BUS_INTERFACE SPLB = mb_plb
PORT GPIO_IO_I = fpga_0_DIP_Switches_8Bits_GPIO_IO_I_pin
END

BEGIN xps_gpio
PARAMETER INSTANCE = LEDs_8Bits
PARAMETER C_ALL_INPUTS = 0
PARAMETER C_GPIO_WIDTH = 8
PARAMETER C_INTERRUPT_PRESENT = 0
PARAMETER C_IS_DUAL = 0
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0x81420000
PARAMETER C_HIGHADDR = 0x8142ffff
BUS_INTERFACE SPLB = mb_plb
PORT GPIO_IO_O = fpga_0_LEDs_8Bits_GPIO_IO_O_pin
END

BEGIN xps_gpio
PARAMETER INSTANCE = Push_Buttons_4Bits
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_GPIO_WIDTH = 4
PARAMETER C_INTERRUPT_PRESENT = 0
PARAMETER C_IS_DUAL = 0
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0x81400000
PARAMETER C_HIGHADDR = 0x8140ffff
BUS_INTERFACE SPLB = mb_plb
PORT GPIO_IO_I = fpga_0_Push_Buttons_4Bits_GPIO_IO_I_pin
END

BEGIN xps_ethernetlite
PARAMETER INSTANCE = Ethernet_Lite
PARAMETER HW_VER = 4.00.a
PARAMETER C_INCLUDE_GLOBAL_BUFFERS = 1
PARAMETER C_BASEADDR = 0x81000000
PARAMETER C_HIGHADDR = 0x8100ffff
BUS_INTERFACE SPLB = mb_plb
PORT PHY_tx_clk = fpga_0_Ethernet_Lite_PHY_tx_clk_pin
PORT PHY_rx_clk = fpga_0_Ethernet_Lite_PHY_rx_clk_pin
PORT PHY_crs = fpga_0_Ethernet_Lite_PHY_crs_pin
PORT PHY_dv = fpga_0_Ethernet_Lite_PHY_dv_pin
PORT PHY_rx_data = fpga_0_Ethernet_Lite_PHY_rx_data_pin
PORT PHY_col = fpga_0_Ethernet_Lite_PHY_col_pin
PORT PHY_rx_er = fpga_0_Ethernet_Lite_PHY_rx_er_pin
PORT PHY_rst_n = fpga_0_Ethernet_Lite_PHY_rst_n_pin
PORT PHY_tx_en = fpga_0_Ethernet_Lite_PHY_tx_en_pin
PORT PHY_tx_data = fpga_0_Ethernet_Lite_PHY_tx_data_pin
PORT PHY_MDC = fpga_0_Ethernet_Lite_PHY_MDC_pin
PORT IP2INTC_Irpt = Ethernet_Lite_IP2INTC_Irpt
PORT PHY_MDIO = fpga_0_Ethernet_Lite_PHY_MDIO_pin
END

BEGIN xps_ps2
PARAMETER INSTANCE = PS2_Mouse_Keyboard
PARAMETER C_IS_DUAL = 1
PARAMETER HW_VER = 1.01.b
PARAMETER C_BASEADDR = 0x86a00000
PARAMETER C_HIGHADDR = 0x86a0ffff
BUS_INTERFACE SPLB = mb_plb
PORT PS2_1_DATA = fpga_0_PS2_Mouse_Keyboard_PS2_1_DATA_pin
PORT PS2_1_CLK = fpga_0_PS2_Mouse_Keyboard_PS2_1_CLK_pin
PORT PS2_2_DATA = fpga_0_PS2_Mouse_Keyboard_PS2_2_DATA_pin
PORT PS2_2_CLK = fpga_0_PS2_Mouse_Keyboard_PS2_2_CLK_pin
END

BEGIN xps_mch_emc
PARAMETER INSTANCE = Micron_RAM
PARAMETER C_NUM_BANKS_MEM = 1
PARAMETER C_NUM_CHANNELS = 0
PARAMETER C_MEM0_WIDTH = 16
PARAMETER C_MAX_MEM_WIDTH = 16
PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
PARAMETER C_SYNCH_MEM_0 = 0
PARAMETER C_TCEDV_PS_MEM_0 = 70000
PARAMETER C_TAVDV_PS_MEM_0 = 70000
PARAMETER C_THZCE_PS_MEM_0 = 8000
PARAMETER C_THZOE_PS_MEM_0 = 8000
PARAMETER C_TWC_PS_MEM_0 = 70000
PARAMETER C_TWP_PS_MEM_0 = 45000
PARAMETER C_TLZWE_PS_MEM_0 = 10000
PARAMETER HW_VER = 3.01.a
PARAMETER C_MEM0_BASEADDR = 0x82000000
PARAMETER C_MEM0_HIGHADDR = 0x82ffffff
BUS_INTERFACE SPLB = mb_plb
PORT RdClk = clk_66_6667MHz
PORT Mem_DQ_I = net_bsbassign35
PORT Mem_DQ_O = net_bsbassign51
PORT Mem_DQ_T = net_bsbassign67
PORT Mem_A = net_bsbassign0
PORT Mem_CEN = net_bsbassign34
PORT Mem_OEN = net_bsbassign83
PORT Mem_WEN = net_bsbassign84
PORT Mem_BEN = net_bsbassign32
END

BEGIN d_usb_epp_dstm
PARAMETER INSTANCE = Digilent_Usb_Epp
PARAMETER C_NUM_USER_REGS = 256
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0xcbc00000
PARAMETER C_HIGHADDR = 0xcbc0ffff
BUS_INTERFACE SPLB = mb_plb
PORT IFCLK = fpga_0_Digilent_Usb_Epp_IFCLK_pin
PORT STMEN = fpga_0_Digilent_Usb_Epp_STMEN_pin
PORT FLAGA = fpga_0_Digilent_Usb_Epp_FLAGA_pin
PORT FLAGB = fpga_0_Digilent_Usb_Epp_FLAGB_pin
PORT FLAGC = fpga_0_Digilent_Usb_Epp_FLAGC_pin
PORT SLRD = fpga_0_Digilent_Usb_Epp_SLRD_pin
PORT SLWR = fpga_0_Digilent_Usb_Epp_SLWR_pin
PORT SLOE = fpga_0_Digilent_Usb_Epp_SLOE_pin
PORT FIFOADR = fpga_0_Digilent_Usb_Epp_FIFOADR_pin
PORT PKTEND = fpga_0_Digilent_Usb_Epp_PKTEND_pin
PORT EPPRST = fpga_0_Digilent_Usb_Epp_EPPRST_pin
PORT DB = fpga_0_Digilent_Usb_Epp_DB_pin
END

BEGIN mem_bus_mux
PARAMETER INSTANCE = mem_bus_mux_0
PARAMETER HW_VER = 1.00.a
PORT ADDR_RAM_IN = net_bsbassign0
PORT DQ_O_RAM = net_bsbassign51
PORT DQ_T_RAM = net_bsbassign67
PORT DQ_I_RAM = net_bsbassign35
PORT BEN_RAM_I = net_bsbassign32
PORT CEN_RAM_I = net_bsbassign34
PORT OEN_RAM_I = net_bsbassign83
PORT WEN_RAM_I = net_bsbassign84
PORT MEM_ADDR = fpga_0_mem_bus_mux_0_MEM_ADDR_pin
PORT DQ = fpga_0_mem_bus_mux_0_DQ_pin
PORT MEM_OEN = fpga_0_mem_bus_mux_0_MEM_OEN_pin
PORT MEM_WEN = fpga_0_mem_bus_mux_0_MEM_WEN_pin
PORT RAM_CEN_O = fpga_0_mem_bus_mux_0_RAM_CEN_O_pin
PORT RAM_BEN_O = fpga_0_mem_bus_mux_0_RAM_BEN_O_pin
PORT FLASH_ADDR = fpga_0_mem_bus_mux_0_FLASH_ADDR_pin
PORT FLASH_CEN_O = fpga_0_mem_bus_mux_0_FLASH_CEN_O_pin
PORT FLASH_RPN_O = fpga_0_mem_bus_mux_0_FLASH_RPN_O_pin
PORT QUAD_SPI_C_O = fpga_0_mem_bus_mux_0_QUAD_SPI_C_O_pin
PORT QUAD_SPI_S_O = fpga_0_mem_bus_mux_0_QUAD_SPI_S_O_pin
PORT MOSI_QUAD_SPI = fpga_0_mem_bus_mux_0_MOSI_QUAD_SPI_pin
END

BEGIN xps_timer
PARAMETER INSTANCE = xps_timer_0
PARAMETER C_COUNT_WIDTH = 32
PARAMETER C_ONE_TIMER_ONLY = 0
PARAMETER HW_VER = 1.02.a
PARAMETER C_BASEADDR = 0x83c00000
PARAMETER C_HIGHADDR = 0x83c0ffff
BUS_INTERFACE SPLB = mb_plb
PORT Interrupt = xps_timer_0_Interrupt
END

BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
PARAMETER C_CLKIN_FREQ = 100000000
PARAMETER C_CLKOUT0_FREQ = 66666666
PARAMETER C_CLKOUT0_PHASE = 0
PARAMETER C_CLKOUT0_GROUP = NONE
PARAMETER C_CLKOUT0_BUF = TRUE
PARAMETER C_EXT_RESET_HIGH = 1
PARAMETER HW_VER = 4.03.a
PORT CLKIN = CLK_S
PORT CLKOUT0 = clk_66_6667MHz
PORT RST = sys_rst_s
PORT LOCKED = Dcm_all_locked
END

BEGIN mdm
PARAMETER INSTANCE = mdm_0
PARAMETER C_MB_DBG_PORTS = 1
PARAMETER C_USE_UART = 1
PARAMETER HW_VER = 2.00.b
PARAMETER C_BASEADDR = 0x84400000
PARAMETER C_HIGHADDR = 0x8440ffff
BUS_INTERFACE SPLB = mb_plb
BUS_INTERFACE MBDEBUG_0 = microblaze_0_mdm_bus
PORT Debug_SYS_Rst = Debug_SYS_Rst
END

BEGIN proc_sys_reset
PARAMETER INSTANCE = proc_sys_reset_0
PARAMETER C_EXT_RESET_HIGH = 1
PARAMETER HW_VER = 3.00.a
PORT Slowest_sync_clk = clk_66_6667MHz
PORT Ext_Reset_In = sys_rst_s
PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
PORT Dcm_locked = Dcm_all_locked
PORT MB_Reset = mb_reset
PORT Bus_Struct_Reset = sys_bus_reset
PORT Peripheral_Reset = sys_periph_reset
END

BEGIN xps_intc
PARAMETER INSTANCE = xps_intc_0
PARAMETER HW_VER = 2.01.a
PARAMETER C_BASEADDR = 0x81800000
PARAMETER C_HIGHADDR = 0x8180ffff
BUS_INTERFACE SPLB = mb_plb
PORT Intr = RS232_Uart_1_Interrupt & Ethernet_Lite_IP2INTC_Irpt & xps_timer_0_Interrupt
PORT Irq = microblaze_0_Interrupt
END

[golson]

I pretty sure that lwip does not support Ethernet lite which is in your design.   I would try to use the other ethernet device.  like a Soft or hard

TEMAC.

[spilgeo]

Thank you for your reply....

I tried to use the xapp1026.pdf so there used the EthernetLite...But i dod what it said, like it said but i have no connection... The light in the ethernet lights the connection in my PC is done but without really connection...I put my IP 192.168.1.11 and the other like the code said but i took an signal that "Without access"..I can't understand why...Anyone one idea?

From this file zip i used the sp601_Plb because it is closer than my board....