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[peterjheijnen]

I am confused about the number of requests MPMC can queue per NPI port because in the datasheet I found the following bits of information:

- The MPMC System parameter 'C_MAX_REQ_ALLOWED' has a fixed value of '1'.

- In the part about 'Restrictions on block RAM (BRAM) FIFOs' it says 'By relying on the current MPMC architecture maximum of two pending transactions for a particular port'

Can anyone help me to find the correct number?

Peter.

[ivan.mironenko]

Hi Peter,

I think that the first parameter (C_MAX_REQ_ALLOWED) refers to some inner structures of the MPMC.

If you want to use NPI port, you should refer to 'Restrictions on block RAM (BRAM) FIFOs', at least that's what I have done :)

Best regards,

Ivan

[peterjheijnen]

Hi Ivan,

What you wrote has been confirmed by Xilinx. 

Thank you.

Regards,

Peter.