01-19-2010 04:34 AM
I am confused about the number of requests MPMC can queue per NPI port because in the datasheet I found the following bits of information:
- The MPMC System parameter 'C_MAX_REQ_ALLOWED' has a fixed value of '1'.
- In the part about 'Restrictions on block RAM (BRAM) FIFOs' it says 'By relying on the current MPMC architecture maximum of two pending transactions for a particular port'
Can anyone help me to find the correct number?
01-20-2010 05:40 AM
I think that the first parameter (C_MAX_REQ_ALLOWED) refers to some inner structures of the MPMC.
If you want to use NPI port, you should refer to 'Restrictions on block RAM (BRAM) FIFOs', at least that's what I have done :)