axi light slave aclk frequency

mairt · ‎12-19-2011

Hi All,

I'm having a problem that i need to know the clock frequency of my axi light slave in my custom IP-Core.

I looked into the "platform specification reference manual" on page 50 where the optional parameter C_<BUSIF>_ACLK_FREQ_HZ is listed. This parameter is stated that it gives the "Frequency (Hertz) of <BUSIF>_ACLK input".

In order to read this value I created a parameter in my mpd by adding the following line:

PARAMETER C_S_AXI_REG_ACLK_FREQ_HZ = 123, DT = INTEGER, BUS = S_AXI_REG

Then I added the generic C_S_AXI_MAC_REG_ACLK_FREQ_HZ : integer := 20; in my design which now should now be filled with the correct clock frequency in Hz of the clock which is connected to REG_ACLK. The problem now is that the generic is only set to 123 (the init value of the parameter) instead of to be filled with the actual clock frequency of 50000000Hz (50Mhz)!

I hope that somebody is able to help me!

greetings

Thomas

johnmcd · ‎02-01-2008

That should work. Mind you, I see that your mpd parameter contains S_AXI_REG where your vhdl generic is S_AXI_MAC_REG. The quickest way to verify the values passed in are once you start generating the netlist, look in the project's hdl directory and you should see a wrapper created for your core. Verify the correct value is set for C_S_AXI_REG_ACLK_FREQ_HZ. If this is correct, then make sure the generic within your core's hdl matches.

I presume you have a line in your mpd something like 'BUS_INTERFACE BUS = S_AXI_REG, BUS_STD = AXI, BUS_TYPE = SLAVE'.

mairt · ‎12-19-2011

Hi!

Thank's for your reply! I'm sorry that i posted the wrong name of the generic! It is of course named C_S_AXI_REG_ACLK_FREQ_HZ! As you also mentioned I have the line

'BUS_INTERFACE BUS = S_AXI_REG, BUS_STD = AXI, BUS_TYPE = SLAVE' in my mpd.

The thing is that the initial value (C_S_AXI_REG_ACLK_FREQ_HZ = 123) from my parameter in the mpd is successfully written down to my vhdl top level entity generic. The problem now is that the parameter should be filled with the correct freuency of the aclk port of my bus interface. I actually assumed that the parameter in the mpd is automatically filled with the correct freuency by executing a xilinx tcl procedure during compile time.

This are the interesting parts of my mpd:

BUS_INTERFACE BUS = S_AXI_REG, BUS_STD = AXI, BUS_TYPE = SLAVE

PARAMETER C_S_AXI_REG_NUM_ADDR_RANGES = 2, DT = integer, BUS = S_AXI_REG, ASSIGNMENT = CONSTANT
PARAMETER C_S_AXI_REG_RNG0_BASEADDR = 0xffffffff, DT = std_logic_vector, BUS = S_AXI_REG, ADDRESS = BASE, PAIR = C_S_AXI_REG_RNG0_HIGHADDR, MIN_SIZE = 0x2000, ASSIGNMENT = REQUIRE
PARAMETER C_S_AXI_REG_RNG0_HIGHADDR = 0x00000000, DT = std_logic_vector, BUS = S_AXI_REG, ADDRESS = HIGH, PAIR = C_S_AXI_REG_RNG0_BASEADDR, ASSIGNMENT = REQUIRE
PARAMETER C_S_AXI_REG_RNG1_BASEADDR = 0xffffffff, DT = std_logic_vector, BUS = S_AXI_REG, ADDRESS = BASE, PAIR = C_S_AXI_REG_RNG1_HIGHADDR, MIN_SIZE = 0x10, ASSIGNMENT = REQUIRE
PARAMETER C_S_AXI_REG_RNG1_HIGHADDR = 0x00000000, DT = std_logic_vector, BUS = S_AXI_REG, ADDRESS = HIGH, PAIR = C_S_AXI_REG_RNG1_BASEADDR, ASSIGNMENT = REQUIRE

PARAMETER C_S_AXI_REG_DATA_WIDTH = 32, DT = integer, BUS = S_AXI_REG, ASSIGNMENT = CONSTANT
PARAMETER C_S_AXI_REG_ADDR_WIDTH = 32, DT = integer, BUS = S_AXI_REG, ASSIGNMENT = CONSTANT
PARAMETER C_S_AXI_REG_ACLK_FREQ_HZ = 123, DT = integer, BUS = S_AXI_REG, ASSIGNMENT = UPDATE
PARAMETER C_S_AXI_REG_USE_WSTRB = 1, DT = integer, ASSIGNMENT = CONSTANT, BUS = S_AXI_REG
PARAMETER C_S_AXI_REG_DPHASE_TIMEOUT = 0, DT = integer, RANGE = (0:512), BUS = S_AXI_REG
PARAMETER C_S_AXI_REG_PROTOCOL = AXI4LITE, DT = string, BUS = S_AXI_REG, ASSIGNMENT = CONSTANT, TYPE = NON_HDL

#port definitions

PORT REG_ACLK = "", DIR = I, SIGIS = CLK, BUS = S_AXI_REG
PORT REG_ARESETN = ARESETN, DIR = I, SIGIS = RST, BUS = S_AXI_REG
PORT REG_ARVALID = ARVALID, DIR = I, BUS = S_AXI_REG
PORT REG_AWVALID = AWVALID, DIR = I, BUS = S_AXI_REG
PORT REG_BREADY = BREADY, DIR = I, BUS = S_AXI_REG
PORT REG_RREADY = RREADY, DIR = I, BUS = S_AXI_REG
PORT REG_WVALID = WVALID, DIR = I, BUS = S_AXI_REG
PORT REG_ARADDR = ARADDR, DIR = I, VEC = [C_S_AXI_REG_ADDR_WIDTH-1:0], ENDIAN = LITTLE, BUS = S_AXI_REG
PORT REG_AWADDR = AWADDR, DIR = I, VEC = [C_S_AXI_REG_ADDR_WIDTH-1:0], ENDIAN = LITTLE, BUS = S_AXI_REG
PORT REG_WDATA = WDATA, DIR = I, VEC = [C_S_AXI_REG_DATA_WIDTH-1:0], ENDIAN = LITTLE, BUS = S_AXI_REG
PORT REG_WSTRB = WSTRB, DIR = I, VEC = [(C_S_AXI_REG_DATA_WIDTH/8)-1:0], ENDIAN = LITTLE, BUS = S_AXI_REG
PORT REG_ARREADY = ARREADY, DIR = O, BUS = S_AXI_REG
PORT REG_AWREADY = AWREADY, DIR = O, BUS = S_AXI_REG
PORT REG_BVALID = BVALID, DIR = O, BUS = S_AXI_REG
PORT REG_RVALID = RVALID, DIR = O, BUS = S_AXI_REG
PORT REG_WREADY = WREADY, DIR = O, BUS = S_AXI_REG
PORT REG_BRESP = BRESP, DIR = O, VEC = [1:0], BUS = S_AXI_REG
PORT REG_RDATA = RDATA, DIR = O, VEC = [C_S_AXI_REG_DATA_WIDTH-1:0], ENDIAN = LITTLE, BUS = S_AXI_REG
PORT REG_RRESP = RRESP, DIR = O, VEC = [1:0], BUS = S_AXI_REG

johnmcd · ‎02-01-2008

I tried it without ASSIGNMENT=UPDATE but that should make no difference since 'UPDATE' is the default.

Once you start running 'generate netlist' does the file <project>\hdl\my_core_wrapper.vhd have the C_S_AXI_REG_ACLK_FREQ_HZ generic set to the correct value?

mairt · ‎12-19-2011

Yes the my_register_wrapper.vhd states C_S_AXI_REG_ACLK_FREQ_HZ => 123, which is the initial value from the mpd PARAMETER. So therefore in this example it was changed from 20 to 123. So writing the parameter down to the generic works. The problem is that the parameter is not filled with the clock freuqency. So therefore I expected to read 50000000 Hz instead of 123 in the generic!

mairt · ‎12-19-2011

Is there maybe an other way than using the C_<INTERCONNECT>_ACLK_FREQ_HZ to access the bus frequency in my

custom IP-Core. The reason to access this frequency is actually to just check if the connected frequency is 50Mhz. I just want to return an error if the frequency is different. So maybe there is a prewritten tcl procedure which is returning me this frequency and i can do the error handling in my mpd? I already searched in the xilinx tcl libraries but was not able to find anything.

greetings

Thomas