06-21-2012 05:33 AM
I want to understand how does the BRAM with dual ports works. how it avoid two processors to write at the same time or to the same address.
each controller connected to one plb(bus), so it doesn't know what the other controller does.
I assume that the bram outputs a busy flag to the controllers, but in the list of the signals I don't see this signal, so how the controllers work?
06-21-2012 08:32 AM
Nothing in the dual port BRAM prevents you from doing something stupid.
That is up to you to decide what you need, and then to design it so that it is prevented (or write a program to check, so you do not try to write to the same location, at the same time).
Xilinx San Jose
06-21-2012 09:45 AM
First, thanks for your reply
I wrote a c code that causes both processors read and write the same location and the program worked excellent,
According to you, I realize this was in case and if I don't add anything to the shared memory the processors may also try to write together and the program gets stuck or give incorrect results. Is that right? There is no solution built in the shared memory that provided?
06-21-2012 09:55 AM
If both ports try to write the same location, one will win, or one will lose, or both will lose (the wrong value will be written).
Nothing will stop. The BRAM doesn't care. Only your program will care, if it expects to get the same data back that it wrote (it may not).
The BRAM is a 8T SRAM cell: (not a pseudo dual port)
As each port has its own pair of data, and data_b series access transistors to the cell, as long as you are not trying to write the cell, these two ports will operate independently, properly.
Xilinx San Jose
06-21-2012 11:08 AM
One more question, I did not understand the first sentence, what does that mean that one will win or lose - is simply not writing as he wants or he does not write at all? How the BRAM determines what to do in the event of a collision? Do you have a link for a detailed explanation on this issue?
thanks a lot