Embedded Development Tools

[bensaad.adel]

i'm new with embedded system design and Xilinx tools.

I should make a simple application of image processing with the xilinx product Spartan-3 XCS200.

I'm workink with the Xilinx ISE Design Suite 10.1

I am able to run a C program to do some small processes on the image ( a PGM file)

this is a part of the code:

#include <stdio.h>
#include <stdlib.h>

int main()
{
	FILE *stream, *stream2;
	char ch[50];
	unsigned char pix, image_src[32][32], image_dest[32][32];
	int lig = 0, col = 0, ligne=0;
		
	if( (stream = fopen("source.pgm","rt")) == NULL )
	 {exit(1);}
	if( (stream2 = fopen("dest.pgm","w")) == NULL )
	{exit(1);}

	stream2 = fopen("dest.pgm","a+");
	for(lig=0; lig<32; lig++)
	 for(col=0; col<32; col++)
			 fprintf(stream2, "%d\n", image_dest[lig][col]);
	fclose(stream);
	fclose(stream2);
	return 0;
}

 the code runs perfectly whith Turbo c++ or Visual c++, and i have a file output.PGM as a result.

My problem is that i can not see any result after downloading the bit file to the FPGA board.

I think that the problem comes from the use of fopen, fscanf and fprintf .

my code must have a file img_input.PGM as input and a file img_output.PGM as output.

how can i download the input PGM file to the FPGA board ?

and where i will get the otput one?

thanks.

ADEL.

[bensaad.adel]

this is my system.mhs file:

# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 10.1 Build EDK_K.15
# Wed Dec 16 09:05:12 2009
# Target Board:  Xilinx Spartan-3 Starter Board Rev E
# Family:    spartan3
# Device:    xc3s200
# Package:   ft256
# Speed Grade:  -4
# Processor: microblaze_0
# System clock frequency: 50.00 MHz
# On Chip Memory :   8 KB
# Total Off Chip Memory :   1 MB
# - SRAM =   1 MB
# ##############################################################################
 PARAMETER VERSION = 2.1.0


 PORT fpga_0_RS232_RX_pin = fpga_0_RS232_RX, DIR = I
 PORT fpga_0_RS232_TX_pin = fpga_0_RS232_TX, DIR = O
 PORT fpga_0_SRAM_Mem_A_pin = fpga_0_SRAM_Mem_A, DIR = O, VEC = [12:29]
 PORT fpga_0_SRAM_Mem_DQ_pin = fpga_0_SRAM_Mem_DQ, DIR = IO, VEC = [0:31]
 PORT fpga_0_SRAM_Mem_OEN_pin = fpga_0_SRAM_Mem_OEN, DIR = O, VEC = [0:0]
 PORT fpga_0_SRAM_Mem_CEN_pin = fpga_0_SRAM_Mem_CEN, DIR = O, VEC = [0:0]
 PORT fpga_0_SRAM_Mem_CEN_1_pin = fpga_0_SRAM_Mem_CEN, DIR = O, VEC = [0:0]
 PORT fpga_0_SRAM_Mem_WEN_pin = fpga_0_SRAM_Mem_WEN, DIR = O
 PORT fpga_0_SRAM_Mem_BEN_pin = fpga_0_SRAM_Mem_BEN, DIR = O, VEC = [0:3]
 PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 50000000
 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 1, SIGIS = RST


BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER C_INTERCONNECT = 1
 PARAMETER HW_VER = 7.10.a
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_AREA_OPTIMIZED = 1
 BUS_INTERFACE DLMB = dlmb
 BUS_INTERFACE ILMB = ilmb
 BUS_INTERFACE DPLB = mb_plb
 BUS_INTERFACE IPLB = mb_plb
 BUS_INTERFACE DEBUG = microblaze_0_dbg
 PORT MB_RESET = mb_reset
END

BEGIN plb_v46
 PARAMETER INSTANCE = mb_plb
 PARAMETER HW_VER = 1.02.a
 PORT PLB_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb
 PARAMETER HW_VER = 1.00.a
 PORT LMB_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb
 PARAMETER HW_VER = 1.00.a
 PORT LMB_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr
 PARAMETER HW_VER = 2.10.a
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = dlmb
 BUS_INTERFACE BRAM_PORT = dlmb_port
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr
 PARAMETER HW_VER = 2.10.a
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = ilmb
 BUS_INTERFACE BRAM_PORT = ilmb_port
END

BEGIN bram_block
 PARAMETER INSTANCE = lmb_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = ilmb_port
 BUS_INTERFACE PORTB = dlmb_port
END

BEGIN xps_uartlite
 PARAMETER INSTANCE = RS232
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BAUDRATE = 9600
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_ODD_PARITY = 0
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_SPLB_CLK_FREQ_HZ = 50000000
 PARAMETER C_BASEADDR = 0x84000000
 PARAMETER C_HIGHADDR = 0x8400ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT RX = fpga_0_RS232_RX
 PORT TX = fpga_0_RS232_TX
END

BEGIN xps_mch_emc
 PARAMETER INSTANCE = SRAM
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_MCH_PLB_CLK_PERIOD_PS = 20000
 PARAMETER C_NUM_BANKS_MEM = 1
 PARAMETER C_TCEDV_PS_MEM_0 = 10000
 PARAMETER C_TWC_PS_MEM_0 = 8000
 PARAMETER C_TAVDV_PS_MEM_0 = 10000
 PARAMETER C_TWP_PS_MEM_0 = 8000
 PARAMETER C_MEM0_BASEADDR = 0x84100000
 PARAMETER C_MEM0_HIGHADDR = 0x841fffff
 BUS_INTERFACE SPLB = mb_plb
 PORT Mem_A = fpga_0_SRAM_Mem_A_split
 PORT Mem_DQ = fpga_0_SRAM_Mem_DQ
 PORT Mem_OEN = fpga_0_SRAM_Mem_OEN
 PORT Mem_CEN = fpga_0_SRAM_Mem_CEN
 PORT Mem_WEN = fpga_0_SRAM_Mem_WEN
 PORT Mem_BEN = fpga_0_SRAM_Mem_BEN
END

BEGIN util_bus_split
 PARAMETER INSTANCE = SRAM_util_bus_split_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE_IN = 32
 PARAMETER C_LEFT_POS = 12
 PARAMETER C_SPLIT = 30
 PORT Sig = fpga_0_SRAM_Mem_A_split
 PORT Out1 = fpga_0_SRAM_Mem_A
END

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER C_CLKIN_FREQ = 50000000
 PARAMETER C_CLKOUT0_FREQ = 50000000
 PARAMETER C_CLKOUT0_BUF = TRUE
 PARAMETER C_CLKOUT0_PHASE = 0
 PARAMETER C_CLKOUT0_GROUP = NONE
 PORT CLKOUT0 = sys_clk_s
 PORT CLKIN = dcm_clk_s
 PORT LOCKED = Dcm_all_locked
 PORT RST = net_gnd
END

BEGIN mdm
 PARAMETER INSTANCE = debug_module
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_MB_DBG_PORTS = 1
 PARAMETER C_USE_UART = 1
 PARAMETER C_UART_WIDTH = 8
 PARAMETER C_BASEADDR = 0x84400000
 PARAMETER C_HIGHADDR = 0x8440ffff
 BUS_INTERFACE SPLB = mb_plb
 BUS_INTERFACE MBDEBUG_0 = microblaze_0_dbg
 PORT Debug_SYS_Rst = Debug_SYS_Rst
END

BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT Slowest_sync_clk = sys_clk_s
 PORT Dcm_locked = Dcm_all_locked
 PORT Ext_Reset_In = sys_rst_s
 PORT MB_Reset = mb_reset
 PORT Bus_Struct_Reset = sys_bus_reset
 PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
 PORT Peripheral_Reset = sys_periph_reset
END

 and the system.mss file:

 PARAMETER VERSION = 2.2.0


BEGIN OS
 PARAMETER OS_NAME = standalone
 PARAMETER OS_VER = 2.00.a
 PARAMETER PROC_INSTANCE = microblaze_0
 PARAMETER STDIN = RS232
 PARAMETER STDOUT = RS232
END


BEGIN PROCESSOR
 PARAMETER DRIVER_NAME = cpu
 PARAMETER DRIVER_VER = 1.11.a
 PARAMETER HW_INSTANCE = microblaze_0
 PARAMETER COMPILER = mb-gcc
 PARAMETER ARCHIVER = mb-ar
END


BEGIN DRIVER
 PARAMETER DRIVER_NAME = bram
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = dlmb_cntlr
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = bram
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = ilmb_cntlr
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = lmb_bram
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = uartlite
 PARAMETER DRIVER_VER = 1.12.a
 PARAMETER HW_INSTANCE = RS232
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = emc
 PARAMETER DRIVER_VER = 2.00.a
 PARAMETER HW_INSTANCE = SRAM
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = SRAM_util_bus_split_0
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = clock_generator_0
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = uartlite
 PARAMETER DRIVER_VER = 1.12.a
 PARAMETER HW_INSTANCE = debug_module
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = proc_sys_reset_0
END

 

[bassman59]

Embedded programming is nothing like writing a C program for your desktop PC.

Does your embedded system have a filesystem which fopen(), fscanf() et al can access?

[bensaad.adel]

 thanks for your reply.... but i don't understand what do you mean with : " a filesystem which fopen(), fscanf() et al can access?"

but if you mean the file that i will open with fopen, and read ... Yes, i have it: it's a PGM file.

Here is an example of a small image in the plain PGM format.

P2
# feep.pgm
24 7
15
0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
0  3  3  3  3  0  0  7  7  7  7  0  0 11 11 11 11  0  0 15 15 15 15  0
0  3  0  0  0  0  0  7  0  0  0  0  0 11  0  0  0  0  0 15  0  0 15  0
0  3  3  3  0  0  0  7  7  7  0  0  0 11 11 11  0  0  0 15 15 15 15  0
0  3  0  0  0  0  0  7  0  0  0  0  0 11  0  0  0  0  0 15  0  0  0  0
0  3  0  0  0  0  0  7  7  7  7  0  0 11 11 11 11  0  0 15  0  0  0  0
0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0

There is a newline character at the end of each of these lines.

thanx

ADEL.

[bensaad.adel]

there is no one to reply?

help me please !!!

[bassman59]

---

bensaad.adel wrote:

 thanks for your reply.... but i don't understand what do you mean with : " a filesystem which fopen(), fscanf() et al can access?"

but if you mean the file that i will open with fopen, and read ... Yes, i have it: it's a PGM file.

---

I mean: does the FPGA have a filesystem?

[bensaad.adel]

As i say, i'm new with embedded system design and Xilinx tools.

so if you can explain more what is " a file system " on an FPGA, i'll be very grateful

thanks

ADEL.

[bensaad.adel]

I found half of the solution:

The file open, scan, etc. calls require a file system as well as permanent storage . 

A standard MicroBlaze-based system is standalone, and has no OS and filesystem support .

so i must change OS from Standalone to ....

i must go to software->software platform settings, and then i must choose xilkernel as OS and not standalone option.

is it the right way to do? or i make another mistake !!!
if yes, What are the other changes I should do?
remember: i use the XC3S200 Spartan-3 board.

I look forward to receiving your reply.

ADEL
 

[harshalrode]

Hi

I am just attempting to answer your question. This may not  be the desired solution

Your code is running on microblaze. so you need to have filesystem created in the memory(FLASH mostly).

In software platform settings of SDK, you have MFS library and other file systems libraries.

Using them you can create mfs file system of desired folder.

store this mfs in flash.

Then use xilmfs/xilkernel functions to access those files.

I hope this helps.