04-21-2009 02:23 AM
we're having recognition issues trying to build up an embedded system in EDK on a Virtex 5 FX70T using the plbv46_pcie_v3_00_a PLB to PCI express bridge ip core.
We are developing on a custom designed board, but we're confident the hardware is working well, because we managed to bring up the pci express endpoint example solution of the Endpoint Block Plus for PCI Express v1.9 rev 4 with the core generator.
The cores built with core generator are correctly recognized by the host PC, both in 1x and 4x configurations (those supported by our hardware), however when loading the FX70 with the projects built in EDK, adopting the plbv46_pcie_v3_00_a core, the board doesn't even show up in the pci peripheral listing on the host.
We tried in EDK both starting from scratch with a new project or porting to our board the reference design for ml507 in the xapp1040, with the same results: reference clock signals and reset are getting correctly to the core, but the pci express core seem not to be able to complete the link training sequence getting stucked somewhere in. As a result the link up signal is never asserted, and the PPC440 is held in reset.
Anyway the host PC boots up correctly.
Unfortunately we really need PPC in our design, any help in resolving this issue would be greatly appreciated, thanks.