Don't have a Xilinx account yet?

  • Choose to receive important news and product information
  • Gain access to special content
  • Personalize your web experience on Xilinx.com

Create Account

Username

Password

Forgot your password?
XClose Panel
Xilinx Home
Reply
Super Contributor
onkarkk1
Posts: 131
Registered: ‎12-29-2008
0
Accepted Solution

slack is positive but timing errors...

Hi,

I have a design , i have synthesized it and did post place and route static timing analysis using ISE 10.1 , in the statice timing reports it is showing that slack is positive but 2 timing constraints were not met. Is it possible?? please let me know...

 

Thanks in advance,

regards,

Krishna Kishore 

Expert Contributor
bassman59
Posts: 6,177
Registered: ‎02-25-2008
0

Re: slack is positive but timing errors...


onkarkk1 wrote:

Hi,

I have a design , i have synthesized it and did post place and route static timing analysis using ISE 10.1 , in the statice timing reports it is showing that slack is positive but 2 timing constraints were not met. Is it possible?? please let me know...

 

Thanks in advance,

regards,

Krishna Kishore 


Look carefully at the report. Sounds like you have more than one timing constraint, and at least one is failing.

 

-a


----------------------------------------------------------------
Yes, I do this for a living.
Super Contributor
onkarkk1
Posts: 131
Registered: ‎12-29-2008
0

Re: slack is positive but timing errors...

Thank you Bassman,

 

I have set only one timing constraint on clock, as you said i have seen the report clearly and observed some hold violations like this below,

 

and frequency shown by this is the exact frequency at which the design works??

 

 

 

 

Hold Violations: TS_Bus2IP_Clk = PERIOD TIMEGRP "Bus2IP_Clk" 10 ns HIGH 50%;
--------------------------------------------------------------------------------
Hold Violation:         -4.905ns (requirement - (clock path skew + uncertainty - data path))
  Source:               wr_fifo_u_2/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_3 (FF)
  Destination:          wr_fifo_u_2/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.520ns (Levels of Logic = 0)
  Positive Clock Path Skew: 5.196ns (4.198 - -0.998)
  Source Clock:         Bus2IP_Clk_O rising at 0.000ns
  Destination Clock:    Bus2IP_Clk_IBUF rising at 10.000ns
  Clock Uncertainty:    0.229ns

  Clock Uncertainty:          0.229ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.000ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.217ns
    Phase Error (PE):           0.120ns

  Minimum Data Path: wr_fifo_u_2/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_3 to wr_fifo_u_2/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X23Y9.XQ       Tcko                  0.313   wr_fifo_u_2/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc<3>
                                                       wr_fifo_u_2/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_3
    SLICE_X22Y8.BX       net (fanout=1)        0.289   wr_fifo_u_2/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc<3>
    SLICE_X22Y8.CLK      Tckdi       (-Th)     0.082   wr_fifo_u_2/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg<3>
                                                       wr_fifo_u_2/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_3
    -------------------------------------------------  ---------------------------
    Total                                      0.520ns (0.231ns logic, 0.289ns route)
                                                       (44.4% logic, 55.6% route)
--------------------------------------------------------------------------------
Hold Violation:         -4.905ns (requirement - (clock path skew + uncertainty - data path))
  Source:               wr_fifo_u_2/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_1 (FF)
  Destination:          wr_fifo_u_2/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.523ns (Levels of Logic = 0)
  Positive Clock Path Skew: 5.199ns (4.195 - -1.004)
  Source Clock:         Bus2IP_Clk_O rising at 0.000ns
  Destination Clock:    Bus2IP_Clk_IBUF rising at 10.000ns
  Clock Uncertainty:    0.229ns

  Clock Uncertainty:          0.229ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.000ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.217ns
    Phase Error (PE):           0.120ns

  Minimum Data Path: wr_fifo_u_2/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_1 to wr_fifo_u_2/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X19Y4.XQ       Tcko                  0.313   wr_fifo_u_2/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc<1>
                                                       wr_fifo_u_2/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_1
    SLICE_X19Y5.BX       net (fanout=1)        0.289   wr_fifo_u_2/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc<1>
    SLICE_X19Y5.CLK      Tckdi       (-Th)     0.079   wr_fifo_u_2/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg<1>
                                                       wr_fifo_u_2/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_1
    -------------------------------------------------  ---------------------------
    Total                                      0.523ns (0.234ns logic, 0.289ns route)
                                                       (44.7% logic, 55.3% route)
--------------------------------------------------------------------------------
Hold Violation:         -4.902ns (requirement - (clock path skew + uncertainty - data path))
  Source:               rd_fifo_u_2/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_3 (FF)
  Destination:          rd_fifo_u_2/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.520ns (Levels of Logic = 0)
  Positive Clock Path Skew: 5.193ns (4.187 - -1.006)
  Source Clock:         Bus2IP_Clk_O rising at 0.000ns
  Destination Clock:    Bus2IP_Clk_IBUF rising at 10.000ns
  Clock Uncertainty:    0.229ns

  Clock Uncertainty:          0.229ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.000ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.217ns
    Phase Error (PE):           0.120ns

 

Derived Constraint Report
Derived Constraints for TS_Bus2IP_Clk
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_Bus2IP_Clk                  |     10.000ns|      7.123ns|      8.572ns|           74|            0|          838|         1594|
| TS_CLKFX_BUF                  |      6.667ns|          N/A|          N/A|            0|            0|            0|            0|
| TS_CLKFX_BUF_0                |      6.667ns|          N/A|          N/A|            0|            0|            0|            0|
| TS_CLKFX_BUF_1                |      6.667ns|          N/A|          N/A|            0|            0|            0|            0|
| TS_CLKFX_BUF_2                |      6.667ns|          N/A|          N/A|            0|            0|            0|            0|
| TS_CLKFX_BUF_3                |      6.667ns|          N/A|          N/A|            0|            0|            0|            0|
| TS_CLKFX_BUF_4                |      6.667ns|          N/A|          N/A|            0|            0|            0|            0|
| TS_CLKFX_BUF_5                |      6.667ns|          N/A|          N/A|            0|            0|            0|            0|
| TS_CLKFX_BUF_6                |      6.667ns|          N/A|          N/A|            0|            0|            0|            0|
| TS_CLKFX_BUF_7                |      6.667ns|          N/A|          N/A|            0|            0|            0|            0|
| TS_CLKFX_BUF_8                |      6.667ns|          N/A|          N/A|            0|            0|            0|            0|
| TS_CLKFX_BUF_9                |     10.000ns|      8.572ns|          N/A|            0|            0|         1594|            0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

1 constraint not met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock Bus2IP_Clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
Bus2IP_Clk     |    8.572|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 74  Score: 218189

Constraints cover 2432 paths, 0 nets, and 1596 connections

Design statistics:
   Minimum period:   8.572ns{1}   (Maximum frequency: 116.659MHz)

 

 Regards,

Krishna Kishore 

Expert Contributor
golson
Posts: 899
Registered: ‎04-07-2008

Re: slack is positive but timing errors...

[ Edited ]

This is a common problem.  Not a problem with your specific design but the coregen FIFOs that you are using are causing these violations.

 

One way to get past these violations is to write constraints that will TIG ( Timing Ignore these signals ) or maybe use multicycle constraints.

 

Search out AR #30029 on xilinx website for more information.

 

Here are some constraints I wrote that work for my problem maybe they could be used as examples.

 

 

 

 

Slack: -0.778ns (requirement - (data path - clock path skew + uncertainty))

Source: tx_2/tx_2/USER_LOGIC_I/TX_USR_ENV/ipif_intfc/burst_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_7 (FF)

Destination: tx_2/tx_2/USER_LOGIC_I/TX_USR_ENV/ipif_intfc/burst_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_7 (FF)

Requirement: 1.000ns

Data Path Delay: 0.942ns (Levels of Logic = 0)

 

.... 

 

 

 

NET "tx_0/tx_0/USER_LOGIC_I/TX_USR_ENV/ipif_intfc/burst_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc(*)" TIG;

NET "tx_1/tx_1/USER_LOGIC_I/TX_USR_ENV/ipif_intfc/burst_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc(*)" TIG;

NET "tx_2/tx_2/USER_LOGIC_I/TX_USR_ENV/ipif_intfc/burst_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc(*)" TIG;

 

 

You will find that the read and write pointers will cause violations.

 

 

Message Edited by golson on 03-25-2009 06:27 AM
Super Contributor
onkarkk1
Posts: 131
Registered: ‎12-29-2008
0

Re: slack is positive but timing errors...

Hi Golson,

Thanks for your reply,

 

I have used the constraints  in the way you told, then i got rid of some of the warnings but what ever i have cited in my previous mail they didnt go.. i.e.. in my place and route report warnings are like this ...

 

 
WARNING:Route:466 - Unusually high hold time violation detected among 10 connections. The top 20 such instances are
   printed below. The router will continue and try to fix it
    rd_fifo_u_2/BU2/U0/grf.rf/mem/gdm.dm/N7:X -> IP2RFIFO_Data_31_OBUF:G3 -2546
    rd_fifo_u_2/BU2/U0/grf.rf/mem/gdm.dm/N63:X -> IP2RFIFO_Data_17_OBUF:G3 -2332
    rd_fifo_u_2/BU2/U0/grf.rf/mem/gdm.dm/N5:X -> IP2RFIFO_Data_31_OBUF:G2 -2255
    rd_fifo_u_2/BU2/U0/grf.rf/mem/gdm.dm/N43:X -> IP2RFIFO_Data_22_OBUF:G3 -2249
    rd_fifo_u_2/BU2/U0/grf.rf/mem/gdm.dm/N125:X -> IP2RFIFO_Data_1_OBUF:F2 -2172
    rd_fifo_u_2/BU2/U0/grf.rf/mem/gdm.dm/N31:X -> IP2RFIFO_Data_25_OBUF:G3 -2136
    rd_fifo_u_2/BU2/U0/grf.rf/mem/gdm.dm/N23:X -> IP2RFIFO_Data_27_OBUF:G3 -2098
    rd_fifo_u_2/BU2/U0/grf.rf/mem/gdm.dm/N115:X -> IP2RFIFO_Data_1_OBUF:G3 -2088
    rd_fifo_u_2/BU2/U0/grf.rf/mem/gdm.dm/N117:X -> IP2RFIFO_Data_3_OBUF:G2 -2071
    rd_fifo_u_2/BU2/U0/grf.rf/mem/gdm.dm/N21:X -> IP2RFIFO_Data_27_OBUF:G2 -2004

Phase 9: 0 unrouted; (23175)      REAL time: 31 secs

 

------------------------------------------------------------------------------------------------------
  Constraint                                |  Check  | Worst Case |  Best Case | Timing |   Timing   
                                            |         |    Slack   | Achievable | Errors |    Score   
------------------------------------------------------------------------------------------------------
* TS_Bus2IP_Clk = PERIOD TIMEGRP "Bus2IP_Cl | SETUP   |     2.606ns|     7.394ns|       0|           0
  k" 10 ns HIGH 50%                         | HOLD    |    -2.775ns|            |      13|       23175
------------------------------------------------------------------------------------------------------
  TS_CLKFX_BUF_12 = PERIOD TIMEGRP "CLKFX_B | SETUP   |     2.502ns|     7.498ns|       0|           0
  UF_12" TS_Bus2IP_Clk HIGH 50%             | HOLD    |     0.434ns|            |       0|           0
------------------------------------------------------------------------------------------------------
  TS_CLKFX_BUF = PERIOD TIMEGRP "CLKFX_BUF" | N/A     |         N/A|         N/A|     N/A|         N/A
   TS_Bus2IP_Clk / 1.5 HIGH 50%             |         |            |            |        |            
------------------------------------------------------------------------------------------------------
  TS_CLKFX_BUF_0 = PERIOD TIMEGRP "CLKFX_BU | N/A     |         N/A|         N/A|     N/A|         N/A
  F_0" TS_Bus2IP_Clk / 1.5 HIGH 50%         |         |            |            |        |            
------------------------------------------------------------------------------------------------------
  TS_CLKFX_BUF_1 = PERIOD TIMEGRP "CLKFX_BU | N/A     |         N/A|         N/A|     N/A|         N/A
  F_1" TS_Bus2IP_Clk / 1.5 HIGH 50%         |         |            |            |        |            
------------------------------------------------------------------------------------------------------
  TS_CLKFX_BUF_2 = PERIOD TIMEGRP "CLKFX_BU | N/A     |         N/A|         N/A|     N/A|         N/A
  F_2" TS_Bus2IP_Clk / 1.5 HIGH 50%         |         |            |            |        |            
------------------------------------------------------------------------------------------------------
  TS_CLKFX_BUF_3 = PERIOD TIMEGRP "CLKFX_BU | N/A     |         N/A|         N/A|     N/A|         N/A
  F_3" TS_Bus2IP_Clk / 1.5 HIGH 50%         |         |            |            |        |            
------------------------------------------------------------------------------------------------------
  TS_CLKFX_BUF_4 = PERIOD TIMEGRP "CLKFX_BU | N/A     |         N/A|         N/A|     N/A|         N/A
  F_4" TS_Bus2IP_Clk / 1.5 HIGH 50%         |         |            |            |        |            
------------------------------------------------------------------------------------------------------
  TS_CLKFX_BUF_5 = PERIOD TIMEGRP "CLKFX_BU | N/A     |         N/A|         N/A|     N/A|         N/A
  F_5" TS_Bus2IP_Clk / 1.5 HIGH 50%         |         |            |            |        |            
------------------------------------------------------------------------------------------------------
  TS_CLKFX_BUF_6 = PERIOD TIMEGRP "CLKFX_BU | N/A     |         N/A|         N/A|     N/A|         N/A
  F_6" TS_Bus2IP_Clk / 1.5 HIGH 50%         |         |            |            |        |            
------------------------------------------------------------------------------------------------------
  TS_CLKFX_BUF_7 = PERIOD TIMEGRP "CLKFX_BU | N/A     |         N/A|         N/A|     N/A|         N/A
  F_7" TS_Bus2IP_Clk / 1.5 HIGH 50%         |         |            |            |        |            
------------------------------------------------------------------------------------------------------
  TS_CLKFX_BUF_8 = PERIOD TIMEGRP "CLKFX_BU | N/A     |         N/A|         N/A|     N/A|         N/A
  F_8" TS_Bus2IP_Clk / 1.5 HIGH 50%         |         |            |            |        |            
------------------------------------------------------------------------------------------------------
  TS_CLKFX_BUF_9 = PERIOD TIMEGRP "CLKFX_BU | N/A     |         N/A|         N/A|     N/A|         N/A
  F_9" TS_Bus2IP_Clk HIGH 50%               |         |            |            |        |            
------------------------------------------------------------------------------------------------------
  TS_CLKFX_BUF_10 = PERIOD TIMEGRP "CLKFX_B | N/A     |         N/A|         N/A|     N/A|         N/A
  UF_10" TS_Bus2IP_Clk HIGH 50%             |         |            |            |        |            
------------------------------------------------------------------------------------------------------
  TS_CLKFX_BUF_11 = PERIOD TIMEGRP "CLKFX_B | N/A     |         N/A|         N/A|     N/A|         N/A
  UF_11" TS_Bus2IP_Clk HIGH 50%             |         |            |            |        |            
------------------------------------------------------------------------------------------------------


Derived Constraint Report
Derived Constraints for TS_Bus2IP_Clk
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_Bus2IP_Clk                  |     10.000ns|      7.394ns|      7.498ns|           13|            0|          613|         1386|
| TS_CLKFX_BUF                  |      6.667ns|          N/A|          N/A|            0|            0|            0|            0|
| TS_CLKFX_BUF_0                |      6.667ns|          N/A|          N/A|            0|            0|            0|            0|
| TS_CLKFX_BUF_1                |      6.667ns|          N/A|          N/A|            0|            0|            0|            0|
| TS_CLKFX_BUF_2                |      6.667ns|          N/A|          N/A|            0|            0|            0|            0|
| TS_CLKFX_BUF_3                |      6.667ns|          N/A|          N/A|            0|            0|            0|            0|
| TS_CLKFX_BUF_4                |      6.667ns|          N/A|          N/A|            0|            0|            0|            0|
| TS_CLKFX_BUF_5                |      6.667ns|          N/A|          N/A|            0|            0|            0|            0|
| TS_CLKFX_BUF_6                |      6.667ns|          N/A|          N/A|            0|            0|            0|            0|
| TS_CLKFX_BUF_7                |      6.667ns|          N/A|          N/A|            0|            0|            0|            0|
| TS_CLKFX_BUF_8                |      6.667ns|          N/A|          N/A|            0|            0|            0|            0|
| TS_CLKFX_BUF_9                |     10.000ns|          N/A|          N/A|            0|            0|            0|            0|
| TS_CLKFX_BUF_10               |     10.000ns|          N/A|          N/A|            0|            0|            0|            0|
| TS_CLKFX_BUF_11               |     10.000ns|          N/A|          N/A|            0|            0|            0|            0|
| TS_CLKFX_BUF_12               |     10.000ns|      7.498ns|          N/A|            0|            0|         1386|            0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

1 constraint not met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.

 

Regards,

Krishna Kishore 

 

Super Contributor
onkarkk1
Posts: 131
Registered: ‎12-29-2008
0

Re: slack is positive but timing errors...

this is continuation to my mail , constraints i have used are like this ----

 

 NET "rd_fifo_u_2/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc<4>"TIG;
NET "rd_fifo_u_2/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc<1>"TIG;
NET "rd_fifo_u_2/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc<3>"TIG;
NET "rd_fifo_u_2/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc<2>"TIG;
NET "rd_fifo_u_2/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc<0>"TIG;

NET "wr_fifo_u_2/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc<2>"TIG;
NET "wr_fifo_u_2/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc<0>"TIG;
NET "wr_fifo_u_2/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc<1>"TIG;
NET "wr_fifo_u_2/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc<3>"TIG;
NET "wr_fifo_u_2/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc<4>"TIG;

 

but still hold violations are there like ----

---------------------------------------
Hold Violations: TS_Bus2IP_Clk = PERIOD TIMEGRP "Bus2IP_Clk" 10 ns HIGH 50%;
--------------------------------------------------------------------------------
Hold Violation:         -2.775ns (requirement - (clock path skew + uncertainty - data path))
  Source:               rd_fifo_u_2/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM22.SLICEM_F (RAM)
  Destination:          rd_fifo_u_2/BU2/U0/grf.rf/mem/gdm.dm/dout_i_10 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.376ns (Levels of Logic = 1)
  Positive Clock Path Skew: 4.922ns (4.043 - -0.879)
  Source Clock:         Bus2IP_Clk_O rising at 0.000ns
  Destination Clock:    Bus2IP_Clk_IBUF rising at 10.000ns
  Clock Uncertainty:    0.229ns
  Timing Improvement Wizard

  Clock Uncertainty:          0.229ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.000ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.217ns
    Phase Error (PE):           0.120ns

  Minimum Data Path: rd_fifo_u_2/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM22.SLICEM_F to rd_fifo_u_2/BU2/U0/grf.rf/mem/gdm.dm/dout_i_10
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X44Y32.X       Tshcko                1.574   rd_fifo_u_2/BU2/U0/grf.rf/mem/gdm.dm/N47
                                                       rd_fifo_u_2/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM22.WE
                                                       rd_fifo_u_2/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM22.SLICEM_F
    SLICE_X44Y33.G4      net (fanout=1)        0.945   rd_fifo_u_2/BU2/U0/grf.rf/mem/gdm.dm/N47
    SLICE_X44Y33.CLK     Tckg        (-Th)     0.143   IP2RFIFO_Data_21_OBUF
                                                       rd_fifo_u_2/BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1011
                                                       rd_fifo_u_2/BU2/U0/grf.rf/mem/gdm.dm/dout_i_10
    -------------------------------------------------  ---------------------------
    Total                                      2.376ns (1.431ns logic, 0.945ns route)
                                                       (60.2% logic, 39.8% route)
--------------------------------------------------------------------------------
Hold Violation:         -2.774ns (requirement - (clock path skew + uncertainty - data path))
  Source:               rd_fifo_u_2/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM27.SLICEM_F (RAM)
  Destination:          rd_fifo_u_2/BU2/U0/grf.rf/mem/gdm.dm/dout_i_13 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.405ns (Levels of Logic = 1)
  Positive Clock Path Skew: 4.950ns (4.045 - -0.905)
  Source Clock:         Bus2IP_Clk_O rising at 0.000ns
  Destination Clock:    Bus2IP_Clk_IBUF rising at 10.000ns
  Clock Uncertainty:    0.229ns
  Timing Improvement Wizard

  Clock Uncertainty:          0.229ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.000ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.217ns
    Phase Error (PE):           0.120ns

  Minimum Data Path: rd_fifo_u_2/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM27.SLICEM_F to rd_fifo_u_2/BU2/U0/grf.rf/mem/gdm.dm/dout_i_13
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X46Y54.X       Tshcko                1.574   rd_fifo_u_2/BU2/U0/grf.rf/mem/gdm.dm/N57
                                                       rd_fifo_u_2/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM27.WE
                                                       rd_fifo_u_2/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM27.SLICEM_F
    SLICE_X46Y55.G4      net (fanout=1)        0.974   rd_fifo_u_2/BU2/U0/grf.rf/mem/gdm.dm/N57
    SLICE_X46Y55.CLK     Tckg        (-Th)     0.143   IP2RFIFO_Data_18_OBUF
                                                       rd_fifo_u_2/BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1311
                                                       rd_fifo_u_2/BU2/U0/grf.rf/mem/gdm.dm/dout_i_13
    -------------------------------------------------  ---------------------------
    Total                                      2.405ns (1.431ns logic, 0.974ns route)
                                                       (59.5% logic, 40.5% route)
--------------------------------------------------------------------------------
Hold Violation:         -2.588ns (requirement - (clock path skew + uncertainty - data path))
  Source:               rd_fifo_u_2/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM13.SLICEM_F (RAM)
  Destination:          rd_fifo_u_2/BU2/U0/grf.rf/mem/gdm.dm/dout_i_6 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.563ns (Levels of Logic = 1)
  Positive Clock Path Skew: 4.922ns (4.023 - -0.899)
  Source Clock:         Bus2IP_Clk_O rising at 0.000ns
  Destination Clock:    Bus2IP_Clk_IBUF rising at 10.000ns
  Clock Uncertainty:    0.229ns
  Timing Improvement Wizard

  Clock Uncertainty:          0.229ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.000ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.217ns
    Phase Error (PE):           0.120ns

Please guide me to get rid of this situation , i am new to the constraints , i am so much confused.....

 

thanks in advance,

regards,

Krishna Kishore