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[mijung]

Hi all,

I`m trying to add a xps_ethernetlite core to my EDK project (on a ML510). The phy_tx_clk and phy_rx_clk do not meet the timing constraints:

------------------------------------------------------------------------------------------------------
* NET "xps_ethernetlite_0/xps_ethernetlite_ | NETSKEW |    -2.987ns|     4.987ns|       1|        2987
  0/phy_tx_clk_i" MAXSKEW = 2 ns            |         |            |            |        |            
------------------------------------------------------------------------------------------------------
* NET "xps_ethernetlite_0_PHY_rx_clk_pin_IB | NETSKEW |    -0.503ns|     2.503ns|       1|         503
  UF" MAXSKEW = 2 ns                        |         |            |            |        |           

The "XPS Ethernet Lite Media Access Controller (v2.00b)" states "If the global clock buffers are used for TX/RX clocks, then MAXSKEW constraints are not required".

Probably a dump question: How can I enable global clock buffers for TX/RX clocks in EDK?

Thanks a lot, Michael

[prateek_bhatt · Accepted solution]

Hello.

In order to enable global clock buffers for RX and TX clk you will have to bring your EDK design in ISE and in ISE you can use global clock buffers as 

BUFG_inst : BUFG
   port map (
      O => phy_tx_clk_out,     -- Clock buffer output
      I => phy_tx_clk_in         -- Clock buffer input
   );

 phy_tx_clk_in will be your input port in your ISE entity.

phy_tx_clk_out will be the output of the buffer.

This output you can port map to your phy_tx_clk pin in XPS.

Similar will be the procedure for RX clock. 

[mijung]

Hi Prateek,

I also found the following pcore, which can be instantiated within XPS and then hooked up to the pins and the respective signals:

ftp://ftp.xilinx.com/pub/applications/misc/input_buf_v1_00_a.zip

Thanks a lot for your help.

Bye, Michael